Commit 1f944f97 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'tty-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty 

Pull tty/serial updates from Greg KH:
 "Here is the big set of TTY / Serial patches for 5.7-rc1

  Lots of console fixups and reworking in here, serial core tweaks
  (doesn't that ever get old, why are we still creating new serial
  devices?), serial driver updates, line-protocol driver updates, and
  some vt cleanups and fixes included in here as well.

  All have been in linux-next with no reported issues"

* tag 'tty-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (161 commits)
  serial: 8250: Optimize irq enable after console write
  serial: 8250: Fix rs485 delay after console write
  vt: vt_ioctl: fix use-after-free in vt_in_use()
  vt: vt_ioctl: fix VT_DISALLOCATE freeing in-use virtual console
  tty: serial: make SERIAL_SPRD depend on COMMON_CLK
  tty: serial: fsl_lpuart: fix return value checking
  tty: serial: fsl_lpuart: move dma_request_chan()
  ARM: dts: tango4: Make /serial compatible with ns16550a
  ARM: dts: mmp*: Make the serial ports compatible with xscale-uart
  ARM: dts: mmp*: Fix serial port names
  ARM: dts: mmp2-brownstone: Don't redeclare phandle references
  ARM: dts: pxa*: Make the serial ports compatible with xscale-uart
  ARM: dts: pxa*: Fix serial port names
  ARM: dts: pxa*: Don't redeclare phandle references
  serial: omap: drop unused dt-bindings header
  serial: 8250: 8250_omap: Add DMA support for UARTs on K3 SoCs
  serial: 8250: 8250_omap: Work around errata causing spurious IRQs with DMA
  serial: 8250: 8250_omap: Extend driver data to pass FIFO trigger info
  serial: 8250: 8250_omap: Move locking out from __dma_rx_do_complete()
  serial: 8250: 8250_omap: Account for data in flight during DMA teardown
  ...
parents dfabb077 8d5b3054

Documentation/ABI/testing/sysfs-tty

+7 −0
Original line number Diff line number Diff line
@@ -154,3 +154,10 @@ Description: 
		 device specification. For example, when user sets 7bytes on

		 16550A, which has 1/4/8/14 bytes trigger, the RX trigger is

		 automatically changed to 4 bytes.



What:		/sys/class/tty/ttyS0/console

Date:		February 2020

Contact:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Description:

		 Allows user to detach or attach back the given device as

		 kernel console. It shows and accepts a boolean variable.

Documentation/devicetree/bindings/serial/fsl-imx-uart.txt

+4 −0
Original line number Diff line number Diff line
@@ -8,6 +8,10 @@ Required properties: 
Optional properties:

- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works

                  in DCE mode by default.

- fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached

  to the peripheral inverts the signal transmitted or received,

  respectively, and that the peripheral should invert its output/input

  using the INVT/INVR registers.

- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,

  linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485

  you must enable either the "uart-has-rtscts" or the "rts-gpios"

Documentation/devicetree/bindings/serial/fsl-lpuart.txt

+6 −4
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ Required properties: 
    on Vybrid vf610 SoC with 8-bit register organization

  - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated

    on LS1021A SoC with 32-bit big-endian register organization

  - "fsl,ls1028a-lpuart" for lpuart compatible with the one integrated

    on LS1028A SoC with 32-bit little-endian register organization

  - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated

    on i.MX7ULP SoC with 32-bit little-endian register organization

  - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated
@@ -15,10 +17,10 @@ Required properties: 
- reg : Address and length of the register set for the device

- interrupts : Should contain uart interrupt

- clocks : phandle + clock specifier pairs, one for each entry in clock-names

- clock-names : For vf610/ls1021a/imx7ulp, "ipg" clock is for uart bus/baud

  clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used to access

  lpuart controller registers, it also requires "baud" clock for module to

  receive/transmit data.

- clock-names : For vf610/ls1021a/ls1028a/imx7ulp, "ipg" clock is for uart

  bus/baud clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used

  to access lpuart controller registers, it also requires "baud" clock for

  module to receive/transmit data.



Optional properties:

- dmas: A list of two dma specifiers, one for each entry in dma-names.

arch/arm/boot/dts/mmp2-brownstone.dts

+165 −167
Original line number Diff line number Diff line
@@ -19,13 +19,13 @@ 
		device_type = "memory";

		reg = <0x00000000 0x08000000>;

	};

};



	soc {

		apb@d4000000 {

			uart3: uart@d4018000 {

&uart3 {

	status = "okay";

};

			twsi1: i2c@d4011000 {



&twsi1 {

	status = "okay";

	pmic: max8925@3c {

		compatible = "maxium,max8925";
@@ -186,9 +186,7 @@ 
		};

	};

};

			rtc: rtc@d4010000 {



&rtc {

	status = "okay";

};
 
		};

	};

};

arch/arm/boot/dts/mmp2.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -208,8 +208,8 @@ 
				clocks = <&soc_clocks MMP2_CLK_TIMER>;

			};



			uart1: uart@d4030000 {

				compatible = "mrvl,mmp-uart";

			uart1: serial@d4030000 {

				compatible = "mrvl,mmp-uart", "intel,xscale-uart";

				reg = <0xd4030000 0x1000>;

				interrupts = <27>;

				clocks = <&soc_clocks MMP2_CLK_UART0>;
@@ -218,8 +218,8 @@ 
				status = "disabled";

			};



			uart2: uart@d4017000 {

				compatible = "mrvl,mmp-uart";

			uart2: serial@d4017000 {

				compatible = "mrvl,mmp-uart", "intel,xscale-uart";

				reg = <0xd4017000 0x1000>;

				interrupts = <28>;

				clocks = <&soc_clocks MMP2_CLK_UART1>;
@@ -228,8 +228,8 @@ 
				status = "disabled";

			};



			uart3: uart@d4018000 {

				compatible = "mrvl,mmp-uart";

			uart3: serial@d4018000 {

				compatible = "mrvl,mmp-uart", "intel,xscale-uart";

				reg = <0xd4018000 0x1000>;

				interrupts = <24>;

				clocks = <&soc_clocks MMP2_CLK_UART2>;
@@ -238,8 +238,8 @@ 
				status = "disabled";

			};



			uart4: uart@d4016000 {

				compatible = "mrvl,mmp-uart";

			uart4: serial@d4016000 {

				compatible = "mrvl,mmp-uart", "intel,xscale-uart";

				reg = <0xd4016000 0x1000>;

				interrupts = <46>;

				clocks = <&soc_clocks MMP2_CLK_UART3>;

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