synclink_gt: add clock options (1f80769f) · Commits · 戴 / test

drivers/char/synclink_gt.c

+38 −20

Original line number	Diff line number	Diff line
		@@ -298,6 +298,7 @@ struct slgt_info {

		unsigned int rbuf_fill_level;
		unsigned int if_mode;
		unsigned int base_clock;

		/* device status */

		@@ -1156,6 +1157,9 @@ static long set_params32(struct slgt_info info, struct MGSL_PARAMS32 __user ne
		return -EFAULT;

		spin_lock(&info->lock);
		if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
		info->base_clock = tmp_params.clock_speed;
		} else {
		info->params.mode = tmp_params.mode;
		info->params.loopback = tmp_params.loopback;
		info->params.flags = tmp_params.flags;
		@@ -1169,9 +1173,10 @@ static long set_params32(struct slgt_info info, struct MGSL_PARAMS32 __user ne
		info->params.data_bits = tmp_params.data_bits;
		info->params.stop_bits = tmp_params.stop_bits;
		info->params.parity = tmp_params.parity;
		}
		spin_unlock(&info->lock);

		change_params(info);
		program_hw(info);

		return 0;
		}
		@@ -2559,10 +2564,13 @@ static int set_params(struct slgt_info info, MGSL_PARAMS __user new_params)
		return -EFAULT;

		spin_lock_irqsave(&info->lock, flags);
		if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
		info->base_clock = tmp_params.clock_speed;
		else
		memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
		spin_unlock_irqrestore(&info->lock, flags);

		change_params(info);
		program_hw(info);

		return 0;
		}
		@@ -3432,6 +3440,7 @@ static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev
		info->magic = MGSL_MAGIC;
		INIT_WORK(&info->task, bh_handler);
		info->max_frame_size = 4096;
		info->base_clock = 14745600;
		info->rbuf_fill_level = DMABUFSIZE;
		info->port.close_delay = 5*HZ/10;
		info->port.closing_wait = 30*HZ;
		@@ -3779,7 +3788,7 @@ static void enable_loopback(struct slgt_info *info)
		static void set_rate(struct slgt_info *info, u32 rate)
		{
		unsigned int div;
		static unsigned int osc = 14745600;
		unsigned int osc = info->base_clock;

		/* div = osc/rate - 1
		*
		@@ -4083,18 +4092,27 @@ static void async_mode(struct slgt_info *info)
		* 06 CTS IRQ enable
		* 05 DCD IRQ enable
		* 04 RI IRQ enable
		* 03 reserved, must be zero
		* 03 0=16x sampling, 1=8x sampling
		* 02 1=txd->rxd internal loopback enable
		* 01 reserved, must be zero
		* 00 1=master IRQ enable
		*/
		val = BIT15 + BIT14 + BIT0;
		/* JCR[8] : 1 = x8 async mode feature available */
		if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
		((info->base_clock < (info->params.data_rate * 16)) \|\|
		(info->base_clock % (info->params.data_rate * 16)))) {
		/* use 8x sampling */
		val \|= BIT3;
		set_rate(info, info->params.data_rate * 8);
		} else {
		/* use 16x sampling */
		set_rate(info, info->params.data_rate * 16);
		}
		wr_reg16(info, SCR, val);

		slgt_irq_on(info, IRQ_RXBREAK \| IRQ_RXOVER);

		set_rate(info, info->params.data_rate * 16);

		if (info->params.loopback)
		enable_loopback(info);
		}

include/linux/synclink.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -125,6 +125,7 @@
		#define MGSL_MODE_MONOSYNC 3
		#define MGSL_MODE_BISYNC 4
		#define MGSL_MODE_RAW 6
		#define MGSL_MODE_BASE_CLOCK 7

		#define MGSL_BUS_TYPE_ISA 1
		#define MGSL_BUS_TYPE_EISA 2

Admin message