Commit 1f7dbeb5 authored by Douglas Anderson's avatar Douglas Anderson Committed by Bjorn Andersson
Browse files

soc: qcom: rpmh-rsc: Document the register layout better 



Perhaps it's just me, it took a really long time to understand what
the register layout of rpmh-rsc was just from the #defines.  Let's add
a bunch of comments describing which blocks are part of other blocks.

Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarMaulik Shah <mkshah@codeaurora.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200413100321.v4.2.Iaddc29b72772e6ea381238a0ee85b82d3903e5f2@changeid


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 3b5e3d50

drivers/soc/qcom/rpmh-rsc.c

+74 −5
Original line number Diff line number Diff line
@@ -43,14 +43,29 @@ 
#define DRV_NCPT_MASK			0x1F

#define DRV_NCPT_SHIFT			27



/* Register offsets */

/* Offsets for common TCS Registers, one bit per TCS */

#define RSC_DRV_IRQ_ENABLE		0x00

#define RSC_DRV_IRQ_STATUS		0x04

#define RSC_DRV_IRQ_CLEAR		0x08

#define RSC_DRV_CMD_WAIT_FOR_CMPL	0x10

#define RSC_DRV_IRQ_CLEAR		0x08	/* w/o; write 1 to clear */



/*

 * Offsets for per TCS Registers.

 *

 * TCSes start at 0x10 from tcs_base and are stored one after another.

 * Multiply tcs_id by RSC_DRV_TCS_OFFSET to find a given TCS and add one

 * of the below to find a register.

 */

#define RSC_DRV_CMD_WAIT_FOR_CMPL	0x10	/* 1 bit per command */

#define RSC_DRV_CONTROL			0x14

#define RSC_DRV_STATUS			0x18

#define RSC_DRV_CMD_ENABLE		0x1C

#define RSC_DRV_STATUS			0x18	/* zero if tcs is busy */

#define RSC_DRV_CMD_ENABLE		0x1C	/* 1 bit per command */



/*

 * Offsets for per command in a TCS.

 *

 * Commands (up to 16) start at 0x30 in a TCS; multiply command index

 * by RSC_DRV_CMD_OFFSET and add one of the below to find a register.

 */

#define RSC_DRV_CMD_MSGID		0x30

#define RSC_DRV_CMD_ADDR		0x34

#define RSC_DRV_CMD_DATA		0x38
@@ -67,6 +82,60 @@ 
#define CMD_STATUS_ISSUED		BIT(8)

#define CMD_STATUS_COMPL		BIT(16)



/*

 * Here's a high level overview of how all the registers in RPMH work

 * together:

 *

 * - The main rpmh-rsc address is the base of a register space that can

 *   be used to find overall configuration of the hardware

 *   (DRV_PRNT_CHLD_CONFIG). Also found within the rpmh-rsc register

 *   space are all the TCS blocks. The offset of the TCS blocks is

 *   specified in the device tree by "qcom,tcs-offset" and used to

 *   compute tcs_base.

 * - TCS blocks come one after another. Type, count, and order are

 *   specified by the device tree as "qcom,tcs-config".

 * - Each TCS block has some registers, then space for up to 16 commands.

 *   Note that though address space is reserved for 16 commands, fewer

 *   might be present. See ncpt (num cmds per TCS).

 *

 * Here's a picture:

 *

 *  +---------------------------------------------------+

 *  |RSC                                                |

 *  | ctrl                                              |

 *  |                                                   |

 *  | Drvs:                                             |

 *  | +-----------------------------------------------+ |

 *  | |DRV0                                           | |

 *  | | ctrl/config                                   | |

 *  | | IRQ                                           | |

 *  | |                                               | |

 *  | | TCSes:                                        | |

 *  | | +------------------------------------------+  | |

 *  | | |TCS0  |  |  |  |  |  |  |  |  |  |  |  |  |  | |

 *  | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15|  | |

 *  | | |      |  |  |  |  |  |  |  |  |  |  |  |  |  | |

 *  | | +------------------------------------------+  | |

 *  | | +------------------------------------------+  | |

 *  | | |TCS1  |  |  |  |  |  |  |  |  |  |  |  |  |  | |

 *  | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15|  | |

 *  | | |      |  |  |  |  |  |  |  |  |  |  |  |  |  | |

 *  | | +------------------------------------------+  | |

 *  | | +------------------------------------------+  | |

 *  | | |TCS2  |  |  |  |  |  |  |  |  |  |  |  |  |  | |

 *  | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15|  | |

 *  | | |      |  |  |  |  |  |  |  |  |  |  |  |  |  | |

 *  | | +------------------------------------------+  | |

 *  | |                    ......                     | |

 *  | +-----------------------------------------------+ |

 *  | +-----------------------------------------------+ |

 *  | |DRV1                                           | |

 *  | | (same as DRV0)                                | |

 *  | +-----------------------------------------------+ |

 *  |                      ......                       |

 *  +---------------------------------------------------+

 */



static u32 read_tcs_cmd(struct rsc_drv *drv, int reg, int tcs_id, int cmd_id)

{

	return readl_relaxed(drv->tcs_base + RSC_DRV_TCS_OFFSET * tcs_id + reg +

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