Commit 1f66b7ea authored by Roman Li's avatar Roman Li Committed by Alex Deucher
Browse files

drm/amd/display: Fix fclk idle state 



[Why]
The earlier change 'Fix 6x4K displays' led to fclk value
idling at higher DPM level.

[How]
Apply the fix only to respective multi-display configuration.

Signed-off-by: default avatarRoman Li <Roman.Li@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6e11ea9d

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

+9 −1
Original line number Diff line number Diff line
@@ -591,7 +591,15 @@ static void dce11_pplib_apply_display_requirements( 
			dc,

			context->bw.dce.sclk_khz);



	pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;

	/*

	 * As workaround for >4x4K lightup set dcfclock to min_engine_clock value.

	 * This is not required for less than 5 displays,

	 * thus don't request decfclk in dc to avoid impact

	 * on power saving.

	 *

	 */

	pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4)?

			pp_display_cfg->min_engine_clock_khz : 0;



	pp_display_cfg->min_engine_clock_deep_sleep_khz

			= context->bw.dce.sclk_deep_sleep_khz;

CRA Git | Maintained and supported by SUSTech CRA and CCSE