Commit 1f55660f authored by Finley Xiao's avatar Finley Xiao Committed by Heiko Stuebner
Browse files

clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type 



The div offset of some clocks are different from their mux offset
and the COMPOSITE clock-type require that div and mux offset are
the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that.

Signed-off-by: default avatarFinley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 57a20248

drivers/clk/rockchip/clk.c

+6 −3
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
		const char *const *parent_names, u8 num_parents,

		void __iomem *base,

		int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,

		u8 div_shift, u8 div_width, u8 div_flags,

		int div_offset, u8 div_shift, u8 div_width, u8 div_flags,

		struct clk_div_table *div_table, int gate_offset,

		u8 gate_shift, u8 gate_flags, unsigned long flags,

		spinlock_t *lock)
@@ -95,6 +95,9 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
		}



		div->flags = div_flags;

		if (div_offset)

			div->reg = base + div_offset;

		else

			div->reg = base + muxdiv_offset;

		div->shift = div_shift;

		div->width = div_width;
@@ -516,7 +519,7 @@ void __init rockchip_clk_register_branches( 
				ctx->reg_base, list->muxdiv_offset,

				list->mux_shift,

				list->mux_width, list->mux_flags,

				list->div_shift, list->div_width,

				list->div_offset, list->div_shift, list->div_width,

				list->div_flags, list->div_table,

				list->gate_offset, list->gate_shift,

				list->gate_flags, flags, &ctx->lock);

drivers/clk/rockchip/clk.h

+23 −0
Original line number Diff line number Diff line
@@ -407,6 +407,7 @@ struct rockchip_clk_branch { 
	u8				mux_shift;

	u8				mux_width;

	u8				mux_flags;

	int				div_offset;

	u8				div_shift;

	u8				div_width;

	u8				div_flags;
@@ -438,6 +439,28 @@ struct rockchip_clk_branch { 
		.gate_flags	= gf,				\

	}



#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw,	\

			     mf, do, ds, dw, df, go, gs, gf)	\

	{							\

		.id		= _id,				\

		.branch_type	= branch_composite,		\

		.name		= cname,			\

		.parent_names	= pnames,			\

		.num_parents	= ARRAY_SIZE(pnames),		\

		.flags		= f,				\

		.muxdiv_offset	= mo,				\

		.mux_shift	= ms,				\

		.mux_width	= mw,				\

		.mux_flags	= mf,				\

		.div_offset	= do,				\

		.div_shift	= ds,				\

		.div_width	= dw,				\

		.div_flags	= df,				\

		.gate_offset	= go,				\

		.gate_shift	= gs,				\

		.gate_flags	= gf,				\

	}



#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,	\

			go, gs, gf)				\

	{							\

CRA Git | Maintained and supported by SUSTech CRA and CCSE