Commit 1f4ce3b6 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sun5i: gr8: Use common sun5i DTSI 



Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of
the extra nodes defined there actually apply to all of the sun5i family.

Move those into the common DTSI so that all SoCs can benefit from it, and
include the sun5i DTSI.

Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent bea13693

arch/arm/boot/dts/sun5i-gr8-chip-pro.dts

+2 −2
Original line number Diff line number Diff line
@@ -171,7 +171,7 @@ 


&pwm {

	pinctrl-names = "default";

	pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;

	pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;

	status = "disabled";

};
@@ -220,7 +220,7 @@ 


&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;

	pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;

	status = "okay";

};

arch/arm/boot/dts/sun5i-gr8-evb.dts

+2 −2
Original line number Diff line number Diff line
@@ -281,7 +281,7 @@ 


&pwm {

	pinctrl-names = "default";

	pinctrl-0 = <&pwm0_pins_a>;

	pinctrl-0 = <&pwm0_pins>;

	status = "okay";

};
@@ -332,7 +332,7 @@ 


&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;

	pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;

	status = "okay";

};

arch/arm/boot/dts/sun5i-gr8.dtsi

+29 −588
Original line number Diff line number Diff line
@@ -42,429 +42,20 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



#include "sun5i.dtsi"



#include <dt-bindings/clock/sun5i-ccu.h>

#include <dt-bindings/dma/sun4i-a10.h>

#include <dt-bindings/pinctrl/sun4i-a10.h>

#include <dt-bindings/reset/sun5i-ccu.h>



/ {

	interrupt-parent = <&intc>;

	#address-cells = <1>;

	#size-cells = <1>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a8";

			reg = <0x0>;

			clocks = <&ccu CLK_CPU>;

		};

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		osc24M: clk@01c20050 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

			clock-output-names = "osc24M";

		};



		osc32k: clk@0 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

			clock-output-names = "osc32k";

		};

	};



	display-engine {

		compatible = "allwinner,sun5i-a13-display-engine";

		allwinner,pipelines = <&fe0>;

	};



	soc@01c00000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		sram-controller@01c00000 {

			compatible = "allwinner,sun4i-a10-sram-controller";

			reg = <0x01c00000 0x30>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			sram_a: sram@00000000 {

				compatible = "mmio-sram";

				reg = <0x00000000 0xc000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x00000000 0xc000>;

			};



			sram_d: sram@00010000 {

				compatible = "mmio-sram";

				reg = <0x00010000 0x1000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x00010000 0x1000>;



				otg_sram: sram-section@0000 {

					compatible = "allwinner,sun4i-a10-sram-d";

					reg = <0x0000 0x1000>;

					status = "disabled";

				};

			};

		};



		dma: dma-controller@01c02000 {

			compatible = "allwinner,sun4i-a10-dma";

			reg = <0x01c02000 0x1000>;

			interrupts = <27>;

			clocks = <&ccu CLK_AHB_DMA>;

			#dma-cells = <2>;

		};



		nfc: nand@01c03000 {

			compatible = "allwinner,sun4i-a10-nand";

			reg = <0x01c03000 0x1000>;

			interrupts = <37>;

			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 3>;

			dma-names = "rxtx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi0: spi@01c05000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c05000 0x1000>;

			interrupts = <10>;

			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 27>,

			       <&dma SUN4I_DMA_DEDICATED 26>;

			dma-names = "rx", "tx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi1: spi@01c06000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c06000 0x1000>;

			interrupts = <11>;

			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 9>,

			       <&dma SUN4I_DMA_DEDICATED 8>;

			dma-names = "rx", "tx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		tve0: tv-encoder@01c0a000 {

			compatible = "allwinner,sun4i-a10-tv-encoder";

			reg = <0x01c0a000 0x1000>;

			clocks = <&ccu CLK_AHB_TVE>;

			resets = <&ccu RST_TVE>;

			status = "disabled";



			port {

				#address-cells = <1>;

				#size-cells = <0>;



				tve0_in_tcon0: endpoint@0 {

					reg = <0>;

					remote-endpoint = <&tcon0_out_tve0>;

				};

			};

		};



		tcon0: lcd-controller@01c0c000 {

			compatible = "allwinner,sun5i-a13-tcon";

			reg = <0x01c0c000 0x1000>;

			interrupts = <44>;

			resets = <&ccu RST_LCD>;

			reset-names = "lcd";

			clocks = <&ccu CLK_AHB_LCD>,

				 <&ccu CLK_TCON_CH0>,

				 <&ccu CLK_TCON_CH1>;

			clock-names = "ahb",

				      "tcon-ch0",

				      "tcon-ch1";

			clock-output-names = "tcon-pixel-clock";

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				tcon0_in: port@0 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <0>;



					tcon0_in_be0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&be0_out_tcon0>;

					};

				};



				tcon0_out: port@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;



					tcon0_out_tve0: endpoint@1 {

						reg = <1>;

						remote-endpoint = <&tve0_in_tcon0>;

					};

				};

			};

		};



		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;

			clock-names = "ahb", "mmc";

			interrupts = <32>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c10000 0x1000>;

			clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;

			clock-names = "ahb", "mmc";

			interrupts = <33>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;

			clock-names = "ahb", "mmc";

			interrupts = <34>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		usb_otg: usb@01c13000 {

			compatible = "allwinner,sun4i-a10-musb";

			reg = <0x01c13000 0x0400>;

			clocks = <&ccu CLK_AHB_OTG>;

			interrupts = <38>;

			interrupt-names = "mc";

			phys = <&usbphy 0>;

			phy-names = "usb";

			extcon = <&usbphy 0>;

			allwinner,sram = <&otg_sram 1>;

			status = "disabled";



			dr_mode = "otg";

		};



		usbphy: phy@01c13400 {

			#phy-cells = <1>;

			compatible = "allwinner,sun5i-a13-usb-phy";

			reg = <0x01c13400 0x10 0x01c14800 0x4>;

			reg-names = "phy_ctrl", "pmu1";

			clocks = <&ccu CLK_USB_PHY0>;

			clock-names = "usb_phy";

			resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;

			reset-names = "usb0_reset", "usb1_reset";

			status = "disabled";

		};



		ehci0: usb@01c14000 {

			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";

			reg = <0x01c14000 0x100>;

			interrupts = <39>;

			clocks = <&ccu CLK_AHB_EHCI>;

			phys = <&usbphy 1>;

			phy-names = "usb";

			status = "disabled";

		};



		ohci0: usb@01c14400 {

			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";

			reg = <0x01c14400 0x100>;

			interrupts = <40>;

			clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;

			phys = <&usbphy 1>;

			phy-names = "usb";

			status = "disabled";

		};



		spi2: spi@01c17000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c17000 0x1000>;

			interrupts = <12>;

			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 29>,

			       <&dma SUN4I_DMA_DEDICATED 28>;

			dma-names = "rx", "tx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		ccu: clock@01c20000 {

			compatible = "nextthing,gr8-ccu";

			reg = <0x01c20000 0x400>;

			clocks = <&osc24M>, <&osc32k>;

			clock-names = "hosc", "losc";

			#clock-cells = <1>;

			#reset-cells = <1>;

		};



		intc: interrupt-controller@01c20400 {

			compatible = "allwinner,sun4i-a10-ic";

			reg = <0x01c20400 0x400>;

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		pio: pinctrl@01c20800 {

			compatible = "nextthing,gr8-pinctrl";

			reg = <0x01c20800 0x400>;

			interrupts = <28>;

			clocks = <&ccu CLK_APB0_PIO>;

			gpio-controller;

			interrupt-controller;

			#interrupt-cells = <3>;

			#gpio-cells = <3>;



			i2c0_pins_a: i2c0@0 {

				pins = "PB0", "PB1";

				function = "i2c0";

			};



			i2c1_pins_a: i2c1@0 {

				pins = "PB15", "PB16";

				function = "i2c1";

			};



			i2c2_pins_a: i2c2@0 {

				pins = "PB17", "PB18";

				function = "i2c2";

			};



			i2s0_data_pins_a: i2s0-data@0 {

				pins = "PB6", "PB7", "PB8", "PB9";

				function = "i2s0";

			};



			i2s0_mclk_pins_a: i2s0-mclk@0 {

				pins = "PB5";

				function = "i2s0";

			};



			ir0_rx_pins_a: ir0@0 {

				pins = "PB4";

				function = "ir0";

			};



			lcd_rgb666_pins: lcd-rgb666@0 {

				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",

						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",

						 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",

						 "PD24", "PD25", "PD26", "PD27";

				function = "lcd0";

			};



			mmc0_pins_a: mmc0@0 {

				pins = "PF0", "PF1", "PF2", "PF3",

						 "PF4", "PF5";

				function = "mmc0";

				drive-strength = <30>;

			};



			nand_pins_a: nand-base0@0 {

				pins = "PC0", "PC1", "PC2",

						"PC5", "PC8", "PC9", "PC10",

						"PC11", "PC12", "PC13", "PC14",

						"PC15";

				function = "nand0";

			};



			nand_cs0_pins_a: nand-cs@0 {

				pins = "PC4";

				function = "nand0";

			};



			nand_rb0_pins_a: nand-rb@0 {

				pins = "PC6";

				function = "nand0";

			};



			pwm0_pins_a: pwm0@0 {

				pins = "PB2";

				function = "pwm0";

			};



			pwm1_pins: pwm1 {

				pins = "PG13";

				function = "pwm1";

			};



			spdif_tx_pins_a: spdif@0 {

				pins = "PB10";

				function = "spdif";

				bias-pull-up;

			};



			uart1_pins_a: uart1@1 {

				pins = "PG3", "PG4";

				function = "uart1";

			};



			uart1_cts_rts_pins_a: uart1-cts-rts@0 {

				pins = "PG5", "PG6";

				function = "uart1";

			};



			uart2_pins_a: uart2@1 {

				pins = "PD2", "PD3";

				function = "uart2";

			};



			uart2_cts_rts_pins_a: uart2-cts-rts@0 {

				pins = "PD4", "PD5";

				function = "uart2";

			};



			uart3_pins_a: uart3@1 {

				pins = "PG9", "PG10";

				function = "uart3";

			};



			uart3_cts_rts_pins_a: uart3-cts-rts@0 {

				pins = "PG11", "PG12";

				function = "uart3";

			};

		};



		pwm: pwm@01c20e00 {

			compatible = "allwinner,sun5i-a10s-pwm";

			reg = <0x01c20e00 0xc>;
@@ -473,18 +64,6 @@ 
			status = "disabled";

		};



		timer@01c20c00 {

			compatible = "allwinner,sun4i-a10-timer";

			reg = <0x01c20c00 0x90>;

			interrupts = <22>;

			clocks = <&ccu CLK_HOSC>;

		};



		wdt: watchdog@01c20c90 {

			compatible = "allwinner,sun4i-a10-wdt";

			reg = <0x01c20c90 0x10>;

		};



		spdif: spdif@01c21000 {

			#sound-dai-cells = <0>;

			compatible = "allwinner,sun4i-a10-spdif";
@@ -498,15 +77,6 @@ 
			status = "disabled";

		};



		ir0: ir@01c21800 {

			compatible = "allwinner,sun4i-a10-ir";

			clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;

			clock-names = "apb", "ir";

			interrupts = <5>;

			reg = <0x01c21800 0x40>;

			status = "disabled";

		};



		i2s0: i2s@01c22400 {

			#sound-dai-cells = <0>;

			compatible = "allwinner,sun4i-a10-i2s";
@@ -519,168 +89,39 @@ 
			dma-names = "rx", "tx";

			status = "disabled";

		};



		lradc: lradc@01c22800 {

			compatible = "allwinner,sun4i-a10-lradc-keys";

			reg = <0x01c22800 0x100>;

			interrupts = <31>;

			status = "disabled";

	};



		codec: codec@01c22c00 {

			#sound-dai-cells = <0>;

			compatible = "allwinner,sun4i-a10-codec";

			reg = <0x01c22c00 0x40>;

			interrupts = <30>;

			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;

			clock-names = "apb", "codec";

			dmas = <&dma SUN4I_DMA_NORMAL 19>,

			       <&dma SUN4I_DMA_NORMAL 19>;

			dma-names = "rx", "tx";

			status = "disabled";

		};



		rtp: rtp@01c25000 {

			compatible = "allwinner,sun5i-a13-ts";

			reg = <0x01c25000 0x100>;

			interrupts = <29>;

			#thermal-sensor-cells = <0>;

};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu CLK_APB1_UART1>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;

			interrupts = <3>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu CLK_APB1_UART2>;

			status = "disabled";

		};



		uart3: serial@01c28c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28c00 0x400>;

			interrupts = <4>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu CLK_APB1_UART3>;

			status = "disabled";

		};



		i2c0: i2c@01c2ac00 {

			compatible = "allwinner,sun4i-a10-i2c";

			reg = <0x01c2ac00 0x400>;

			interrupts = <7>;

			clocks = <&ccu CLK_APB1_I2C0>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

&ccu {

	compatible = "nextthing,gr8-ccu";

};



		i2c1: i2c@01c2b000 {

			compatible = "allwinner,sun4i-a10-i2c";

			reg = <0x01c2b000 0x400>;

			interrupts = <8>;

			clocks = <&ccu CLK_APB1_I2C1>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};

&pio {

	compatible = "nextthing,gr8-pinctrl";



		i2c2: i2c@01c2b400 {

			compatible = "allwinner,sun4i-a10-i2c";

			reg = <0x01c2b400 0x400>;

			interrupts = <9>;

			clocks = <&ccu CLK_APB1_I2C2>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

	i2s0_data_pins_a: i2s0-data@0 {

		pins = "PB6", "PB7", "PB8", "PB9";

		function = "i2s0";

	};



		timer@01c60000 {

			compatible = "allwinner,sun5i-a13-hstimer";

			reg = <0x01c60000 0x1000>;

			interrupts = <82>, <83>;

			clocks = <&ccu CLK_AHB_HSTIMER>;

	i2s0_mclk_pins_a: i2s0-mclk@0 {

		pins = "PB5";

		function = "i2s0";

	};



		fe0: display-frontend@01e00000 {

			compatible = "allwinner,sun5i-a13-display-frontend";

			reg = <0x01e00000 0x20000>;

			interrupts = <47>;

			clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>,

				 <&ccu CLK_DRAM_DE_FE>;

			clock-names = "ahb", "mod",

				      "ram";

			resets = <&ccu RST_DE_FE>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				fe0_out: port@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;



					fe0_out_be0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&be0_in_fe0>;

					};

				};

			};

	pwm1_pins: pwm1 {

		pins = "PG13";

		function = "pwm1";

	};



		be0: display-backend@01e60000 {

			compatible = "allwinner,sun5i-a13-display-backend";

			reg = <0x01e60000 0x10000>;

			clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,

				 <&ccu CLK_DRAM_DE_BE>;

			clock-names = "ahb", "mod",

				      "ram";

			resets = <&ccu RST_DE_BE>;

			status = "disabled";



			assigned-clocks = <&ccu CLK_DE_BE>;

			assigned-clock-rates = <300000000>;



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				be0_in: port@0 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <0>;



					be0_in_fe0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&fe0_out_be0>;

					};

	spdif_tx_pins_a: spdif@0 {

		pins = "PB10";

		function = "spdif";

		bias-pull-up;

	};



				be0_out: port@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;



					be0_out_tcon0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&tcon0_in_be0>;

					};

				};

			};

		};

	uart1_cts_rts_pins_a: uart1-cts-rts@0 {

		pins = "PG5", "PG6";

		function = "uart1";

	};

};

arch/arm/boot/dts/sun5i.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -159,6 +159,19 @@ 
			#dma-cells = <2>;

		};



		nfc: nand@01c03000 {

			compatible = "allwinner,sun4i-a10-nand";

			reg = <0x01c03000 0x1000>;

			interrupts = <37>;

			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;

			clock-names = "ahb", "mod";

			dmas = <&dma SUN4I_DMA_DEDICATED 3>;

			dma-names = "rxtx";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi0: spi@01c05000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c05000 0x1000>;
@@ -406,6 +419,11 @@ 
				function = "i2c2";

			};



			ir0_rx_pins_a: ir0@0 {

				pins = "PB4";

				function = "ir0";

			};



			lcd_rgb565_pins: lcd_rgb565@0 {

				pins = "PD3", "PD4", "PD5", "PD6", "PD7",

						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
@@ -447,6 +465,24 @@ 
				bias-pull-up;

			};



			nand_pins_a: nand-base0@0 {

				pins = "PC0", "PC1", "PC2",

				       "PC5", "PC8", "PC9", "PC10",

				       "PC11", "PC12", "PC13", "PC14",

				       "PC15";

				function = "nand0";

			};



			nand_cs0_pins_a: nand-cs@0 {

				pins = "PC4";

				function = "nand0";

			};



			nand_rb0_pins_a: nand-rb@0 {

				pins = "PC6";

				function = "nand0";

			};



			spi2_pins_a: spi2@0 {

				pins = "PE1", "PE2", "PE3";

				function = "spi2";
@@ -505,6 +541,15 @@ 
			reg = <0x01c20c90 0x10>;

		};



		ir0: ir@01c21800 {

			compatible = "allwinner,sun4i-a10-ir";

			clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;

			clock-names = "apb", "ir";

			interrupts = <5>;

			reg = <0x01c21800 0x40>;

			status = "disabled";

		};



		lradc: lradc@01c22800 {

			compatible = "allwinner,sun4i-a10-lradc-keys";

			reg = <0x01c22800 0x100>;

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