Commit 1f2dd7bc authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v3.19-rockchip-dts1' of... 

Merge tag 'v3.19-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "first bunch on Rockchip dt changes" from Heiko Stübner:

First hunk of rockchip devicetree patches, containing:
- cpu operating points and supplies
- dma support for spi controllers
- i2s on rk3066 and rk3188
- default core clock settings for rk3288

* tag 'v3.19-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

:
  ARM: dts: rockchip: Add SPI DMA into rk3288.dtsi
  ARM: dts: rockchip: enable init rate for clock
  ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188
  ARM: dts: rockchip: enable DMA on SPI for rk3066 and rk3188
  ARM: dts: rockchip: add cpu supplies to boards
  ARM: dts: rockchip: add operating points and armclk references

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 2c49e025 11bd57b8

arch/arm/boot/dts/rk3066a-bqcurie2.dts

+4 −0
Original line number Diff line number Diff line
@@ -60,6 +60,10 @@ 
	};

};



&cpu0 {

	cpu0-supply = <&vdd_arm>;

};



&i2c1 {

	status = "okay";

	clock-frequency = <400000>;

arch/arm/boot/dts/rk3066a.dtsi

+92 −1
Original line number Diff line number Diff line
@@ -26,11 +26,21 @@ 
		#size-cells = <0>;

		enable-method = "rockchip,rk3066-smp";



		cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x0>;

			operating-points = <

				/* kHz    uV */

				1008000 1075000

				 816000 1025000

				 600000 1025000

				 504000 1000000

				 312000  975000

			>;

			clock-latency = <40000>;

			clocks = <&cru ARMCLK>;

		};

		cpu@1 {

			device_type = "cpu";
@@ -53,6 +63,51 @@ 
		};

	};



	i2s0: i2s@10118000 {

		compatible = "rockchip,rk3066-i2s";

		reg = <0x10118000 0x2000>;

		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2s0_bus>;

		dmas = <&dmac1_s 4>, <&dmac1_s 5>;

		dma-names = "tx", "rx";

		clock-names = "i2s_hclk", "i2s_clk";

		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;

		status = "disabled";

	};



	i2s1: i2s@1011a000 {

		compatible = "rockchip,rk3066-i2s";

		reg = <0x1011a000 0x2000>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2s1_bus>;

		dmas = <&dmac1_s 6>, <&dmac1_s 7>;

		dma-names = "tx", "rx";

		clock-names = "i2s_hclk", "i2s_clk";

		clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;

		status = "disabled";

	};



	i2s2: i2s@1011c000 {

		compatible = "rockchip,rk3066-i2s";

		reg = <0x1011c000 0x2000>;

		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2s2_bus>;

		dmas = <&dmac1_s 9>, <&dmac1_s 10>;

		dma-names = "tx", "rx";

		clock-names = "i2s_hclk", "i2s_clk";

		clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;

		status = "disabled";

	};



	cru: clock-controller@20000000 {

		compatible = "rockchip,rk3066a-cru";

		reg = <0x20000000 0x1000>;
@@ -405,6 +460,42 @@ 
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;

			};

		};



		i2s0 {

			i2s0_bus: i2s0-bus {

				rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;

			};

		};



		i2s1 {

			i2s1_bus: i2s1-bus {

				rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;

			};

		};



		i2s2 {

			i2s2_bus: i2s2-bus {

				rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,

						<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;

			};

		};

	};

};

arch/arm/boot/dts/rk3188-radxarock.dts

+5 −1
Original line number Diff line number Diff line
@@ -118,6 +118,10 @@ 
	};

};



&cpu0 {

	cpu0-supply = <&vdd_arm>;

};



&i2c1 {

	status = "okay";

	clock-frequency = <400000>;
@@ -159,7 +163,7 @@ 
			vdd_arm: REG3 {

				regulator-name = "VDD_ARM";

				regulator-min-microvolt = <875000>;

				regulator-max-microvolt = <1300000>;

				regulator-max-microvolt = <1350000>;

				regulator-always-on;

			};

arch/arm/boot/dts/rk3188.dtsi

+40 −1
Original line number Diff line number Diff line
@@ -26,11 +26,24 @@ 
		#size-cells = <0>;

		enable-method = "rockchip,rk3066-smp";



		cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x0>;

			operating-points = <

				/* kHz    uV */

				1608000 1350000

				1416000 1250000

				1200000 1150000

				1008000 1075000

				 816000  975000

				 600000  950000

				 504000  925000

				 312000  875000

			>;

			clock-latency = <40000>;

			clocks = <&cru ARMCLK>;

		};

		cpu@1 {

			device_type = "cpu";
@@ -65,6 +78,21 @@ 
		};

	};



	i2s0: i2s@1011a000 {

		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";

		reg = <0x1011a000 0x2000>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2s0_bus>;

		dmas = <&dmac1_s 6>, <&dmac1_s 7>;

		dma-names = "tx", "rx";

		clock-names = "i2s_hclk", "i2s_clk";

		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;

		status = "disabled";

	};



	cru: clock-controller@20000000 {

		compatible = "rockchip,rk3188-cru";

		reg = <0x20000000 0x1000>;
@@ -395,6 +423,17 @@ 
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;

			};

		};



		i2s0 {

			i2s0_bus: i2s0-bus {

				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,

						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,

						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,

						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,

						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,

						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;

			};

		};

	};

};

arch/arm/boot/dts/rk3288-evb-rk808.dts

+5 −1
Original line number Diff line number Diff line
@@ -17,6 +17,10 @@ 
	compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";

};



&cpu0 {

	cpu0-supply = <&vdd_cpu>;

};



&i2c0 {

	clock-frequency = <400000>;

	status = "okay";
@@ -44,7 +48,7 @@ 
				regulator-always-on;

				regulator-boot-on;

				regulator-min-microvolt = <750000>;

				regulator-max-microvolt = <1300000>;

				regulator-max-microvolt = <1350000>;

				regulator-name = "vdd_arm";

			};

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