Commit 1f074e67 authored by Rahul Kundu's avatar Rahul Kundu Committed by David S. Miller
Browse files

cxgb4: Add support to catch bits set in INT_CAUSE5 



This commit adds support to catch any bits set in SGE_INT_CAUSE5 for Parity Errors.
F_ERR_T_RXCRC flag is used to ignore that particular bit as it is not considered as fatal.
So, we clear out the bit before looking for error.
This patch now read and report separately all three registers(Cause1, Cause2, Cause5).
Also, checks for errors if any.

Signed-off-by: default avatarRaju Rangoju <rajur@chelsio.com>
Signed-off-by: default avatarRahul Kundu <rahul.kundu@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6e22c604

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+24 −8
Original line number Original line Diff line number Diff line
@@ -4474,7 +4474,7 @@ static void tp_intr_handler(struct adapter *adapter) 
 */

 */

static void sge_intr_handler(struct adapter *adapter)

static void sge_intr_handler(struct adapter *adapter)

{

{

	u64 v;

	u32 v = 0, perr;

	u32 err;

	u32 err;





	static const struct intr_info sge_intr_info[] = {

	static const struct intr_info sge_intr_info[] = {
@@ -4509,13 +4509,29 @@ static void sge_intr_handler(struct adapter *adapter) 
		{ 0 }

		{ 0 }

	};

	};





	v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |

	perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);

		((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);

	if (perr) {

	if (v) {

		v |= perr;

		dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",

		dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",

				(unsigned long long)v);

			  perr);

		t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);

	}

		t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);



	perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);

	if (perr) {

		v |= perr;

		dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",

			  perr);

	}



	if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {

		perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);

		/* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */

		perr &= ~ERR_T_RXCRC_F;

		if (perr) {

			v |= perr;

			dev_alert(adapter->pdev_dev,

				  "SGE Cause5 Parity Error %#x\n", perr);

		}

	}

	}





	v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);

	v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);

drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -487,6 +487,12 @@ 
#define ERROR_QID_M    0x1ffffU

#define ERROR_QID_M    0x1ffffU

#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)

#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)





#define SGE_INT_CAUSE5_A        0x110c



#define ERR_T_RXCRC_S    31

#define ERR_T_RXCRC_V(x) ((x) << ERR_T_RXCRC_S)

#define ERR_T_RXCRC_F    ERR_T_RXCRC_V(1U)



#define HP_INT_THRESH_S    28

#define HP_INT_THRESH_S    28

#define HP_INT_THRESH_M    0xfU

#define HP_INT_THRESH_M    0xfU

#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)

#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)

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