Commit 1ec16991 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_for_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp 

Pull EDAC updates from Borislav Petkov:
 "The usual pile of bugfixes, cleanups and minor driver enhancements.

  Worth noting are the changes to ghes_edac to use a whitelist of
  known-good platforms on which GHES error reporting works relatively
  reliably. By Toshi Kani and Borislav Petkov"

* tag 'edac_for_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  EDAC, sb_edac: Fix missing break in switch
  MAINTAINERS: Split Cavium EDAC entry and add myself
  EDAC, sb_edac: Fix missing DIMM sysfs entries with KNL SNC2/SNC4 mode
  EDAC, skx_edac: Handle systems with segmented PCI busses
  EDAC, thunderx: Remove suspend/resume support
  EDAC, skx_edac: Fix detection of single-rank DIMMs
  EDAC, sb_edac: Don't create a second memory controller if HA1 is not present
  EDAC: Add owner check to the x86 platform drivers
  EDAC: Add helper which returns the loaded platform driver
  EDAC, ghes: Add platform check
  EDAC, ghes: Model a single, logical memory controller
  EDAC, ghes: Remove symbol exports
  EDAC: Handle return value of kasprintf()
parents 7832681b a8e9b186

MAINTAINERS

+7 −1
Original line number Diff line number Diff line
@@ -4906,13 +4906,19 @@ L: linux-edac@vger.kernel.org 
S:	Maintained

F:	drivers/edac/highbank*



EDAC-CAVIUM

EDAC-CAVIUM OCTEON

M:	Ralf Baechle <ralf@linux-mips.org>

M:	David Daney <david.daney@cavium.com>

L:	linux-edac@vger.kernel.org

L:	linux-mips@linux-mips.org

S:	Supported

F:	drivers/edac/octeon_edac*



EDAC-CAVIUM THUNDERX

M:	David Daney <david.daney@cavium.com>

M:	Jan Glauber <jglauber@cavium.com>

L:	linux-edac@vger.kernel.org

S:	Supported

F:	drivers/edac/thunderx_edac*



EDAC-CORE

drivers/edac/amd64_edac.c

+5 −0
Original line number Diff line number Diff line
@@ -3434,9 +3434,14 @@ MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids); 


static int __init amd64_edac_init(void)

{

	const char *owner;

	int err = -ENODEV;

	int i;



	owner = edac_get_owner();

	if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))

		return -EBUSY;



	if (!x86_match_cpu(amd64_cpuids))

		return -ENODEV;

drivers/edac/edac_mc.c

+6 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static LIST_HEAD(mc_devices); 
 * Used to lock EDAC MC to just one module, avoiding two drivers e. g.

 *	apei/ghes and i7core_edac to be used at the same time.

 */

static void const *edac_mc_owner;

static const char *edac_mc_owner;



static struct bus_type mc_bus[EDAC_MAX_MCS];
@@ -701,6 +701,11 @@ unlock: 
}

EXPORT_SYMBOL(edac_mc_find);



const char *edac_get_owner(void)

{

	return edac_mc_owner;

}

EXPORT_SYMBOL_GPL(edac_get_owner);



/* FIXME - should a warning be printed if no error detection? correction? */

int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,

drivers/edac/edac_mc.h

+8 −0
Original line number Diff line number Diff line
@@ -128,6 +128,14 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, 
				   unsigned sz_pvt);



/**

 * edac_get_owner - Return the owner's mod_name of EDAC MC

 *

 * Returns:

 *	Pointer to mod_name string when EDAC MC is owned. NULL otherwise.

 */

extern const char *edac_get_owner(void);



/*

 * edac_mc_add_mc_with_groups() - Insert the @mci structure into the mci

 *	global list and create sysfs entries associated with @mci structure.

 *

drivers/edac/ghes_edac.c

+69 −68
Original line number Diff line number Diff line
@@ -28,10 +28,19 @@ struct ghes_edac_pvt { 
	char msg[80];

};



static LIST_HEAD(ghes_reglist);

static DEFINE_MUTEX(ghes_edac_lock);

static int ghes_edac_mc_num;

static atomic_t ghes_init = ATOMIC_INIT(0);

static struct ghes_edac_pvt *ghes_pvt;



/*

 * Sync with other, potentially concurrent callers of

 * ghes_edac_report_mem_error(). We don't know what the

 * "inventive" firmware would do.

 */

static DEFINE_SPINLOCK(ghes_lock);



/* "ghes_edac.force_load=1" skips the platform check */

static bool __read_mostly force_load;

module_param(force_load, bool, 0);



/* Memory Device - Type 17 of SMBIOS spec */

struct memdev_dmi_entry {
@@ -169,18 +178,26 @@ void ghes_edac_report_mem_error(struct ghes *ghes, int sev, 
	enum hw_event_mc_err_type type;

	struct edac_raw_error_desc *e;

	struct mem_ctl_info *mci;

	struct ghes_edac_pvt *pvt = NULL;

	struct ghes_edac_pvt *pvt = ghes_pvt;

	unsigned long flags;

	char *p;

	u8 grain_bits;



	list_for_each_entry(pvt, &ghes_reglist, list) {

		if (ghes == pvt->ghes)

			break;

	}

	if (!pvt) {

		pr_err("Internal error: Can't find EDAC structure\n");

		return;

	}



	/*

	 * We can do the locking below because GHES defers error processing

	 * from NMI to IRQ context. Whenever that changes, we'd at least

	 * know.

	 */

	if (WARN_ON_ONCE(in_nmi()))

		return;



	spin_lock_irqsave(&ghes_lock, flags);



	mci = pvt->mci;

	e = &mci->error_desc;
@@ -398,10 +415,17 @@ void ghes_edac_report_mem_error(struct ghes *ghes, int sev, 
		       (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,

		       grain_bits, e->syndrome, pvt->detail_location);



	/* Report the error via EDAC API */

	edac_raw_mc_handle_error(type, mci, e);

	spin_unlock_irqrestore(&ghes_lock, flags);

}

EXPORT_SYMBOL_GPL(ghes_edac_report_mem_error);



/*

 * Known systems that are safe to enable this module.

 */

static struct acpi_platform_list plat_list[] = {

	{"HPE   ", "Server  ", 0, ACPI_SIG_FADT, all_versions},

	{ } /* End */

};



int ghes_edac_register(struct ghes *ghes, struct device *dev)

{
@@ -409,8 +433,19 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) 
	int rc, num_dimm = 0;

	struct mem_ctl_info *mci;

	struct edac_mc_layer layers[1];

	struct ghes_edac_pvt *pvt;

	struct ghes_edac_dimm_fill dimm_fill;

	int idx;



	/* Check if safe to enable on this system */

	idx = acpi_match_platform_list(plat_list);

	if (!force_load && idx < 0)

		return 0;



	/*

	 * We have only one logical memory controller to which all DIMMs belong.

	 */

	if (atomic_inc_return(&ghes_init) > 1)

		return 0;



	/* Get the number of DIMMs */

	dmi_walk(ghes_edac_count_dimms, &num_dimm);
@@ -425,26 +460,17 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) 
	layers[0].size = num_dimm;

	layers[0].is_virt_csrow = true;



	/*

	 * We need to serialize edac_mc_alloc() and edac_mc_add_mc(),

	 * to avoid duplicated memory controller numbers

	 */

	mutex_lock(&ghes_edac_lock);

	mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers,

			    sizeof(*pvt));

	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));

	if (!mci) {

		pr_info("Can't allocate memory for EDAC data\n");

		mutex_unlock(&ghes_edac_lock);

		return -ENOMEM;

	}



	pvt = mci->pvt_info;

	memset(pvt, 0, sizeof(*pvt));

	list_add_tail(&pvt->list, &ghes_reglist);

	pvt->ghes = ghes;

	pvt->mci  = mci;

	mci->pdev = dev;

	ghes_pvt	= mci->pvt_info;

	ghes_pvt->ghes	= ghes;

	ghes_pvt->mci	= mci;



	mci->pdev = dev;

	mci->mtype_cap = MEM_FLAG_EMPTY;

	mci->edac_ctl_cap = EDAC_FLAG_NONE;

	mci->edac_cap = EDAC_FLAG_NONE;
@@ -452,36 +478,23 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) 
	mci->ctl_name = "ghes_edac";

	mci->dev_name = "ghes";



	if (!ghes_edac_mc_num) {

		if (!fake) {

	if (fake) {

		pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");

		pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");

		pr_info("work on such system. Use this driver with caution\n");

	} else if (idx < 0) {

		pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");

		pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");

		pr_info("So, the end result of using this driver varies from vendor to vendor.\n");

		pr_info("If you find incorrect reports, please contact your hardware vendor\n");

		pr_info("to correct its BIOS.\n");

			pr_info("This system has %d DIMM sockets.\n",

				num_dimm);

		} else {

			pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");

			pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");

			pr_info("work on such system. Use this driver with caution\n");

		}

		pr_info("This system has %d DIMM sockets.\n", num_dimm);

	}



	if (!fake) {

		/*

		 * Fill DIMM info from DMI for the memory controller #0

		 *

		 * Keep it in blank for the other memory controllers, as

		 * there's no reliable way to properly credit each DIMM to

		 * the memory controller, as different BIOSes fill the

		 * DMI bank location fields on different ways

		 */

		if (!ghes_edac_mc_num) {

		dimm_fill.count = 0;

		dimm_fill.mci = mci;

		dmi_walk(ghes_edac_dmidecode, &dimm_fill);

		}

	} else {

		struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,

						       mci->n_layers, 0, 0, 0);
@@ -497,28 +510,16 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) 
	if (rc < 0) {

		pr_info("Can't register at EDAC core\n");

		edac_mc_free(mci);

		mutex_unlock(&ghes_edac_lock);

		return -ENODEV;

	}



	ghes_edac_mc_num++;

	mutex_unlock(&ghes_edac_lock);

	return 0;

}

EXPORT_SYMBOL_GPL(ghes_edac_register);



void ghes_edac_unregister(struct ghes *ghes)

{

	struct mem_ctl_info *mci;

	struct ghes_edac_pvt *pvt, *tmp;



	list_for_each_entry_safe(pvt, tmp, &ghes_reglist, list) {

		if (ghes == pvt->ghes) {

			mci = pvt->mci;

	mci = ghes_pvt->mci;

	edac_mc_del_mc(mci->pdev);

	edac_mc_free(mci);

			list_del(&pvt->list);

		}

	}

}
 
EXPORT_SYMBOL_GPL(ghes_edac_unregister);

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