drm/i915: Assert requests within a context are submitted in order (1eaa251b) · Commits · 戴 / test

drivers/gpu/drm/i915/gt/intel_lrc.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -1622,6 +1622,7 @@ static bool can_merge_rq(const struct i915_request *prev,
		if (!can_merge_ctx(prev->context, next->context))
		return false;

		GEM_BUG_ON(i915_seqno_passed(prev->fence.seqno, next->fence.seqno));
		return true;
		}

		@@ -2142,6 +2143,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
		GEM_BUG_ON(last &&
		!can_merge_ctx(last->context,
		rq->context));
		GEM_BUG_ON(last &&
		i915_seqno_passed(last->fence.seqno,
		rq->fence.seqno));

		submit = true;
		last = rq;

+11 −0

Original line number	Diff line number	Diff line
		@@ -737,6 +737,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
		RCU_INIT_POINTER(rq->timeline, tl);
		RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
		rq->hwsp_seqno = tl->hwsp_seqno;
		GEM_BUG_ON(i915_request_completed(rq));

		rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */

		@@ -1284,6 +1285,16 @@ __i915_request_add_to_timeline(struct i915_request *rq)
		prev = to_request(__i915_active_fence_set(&timeline->last_request,
		&rq->fence));
		if (prev && !i915_request_completed(prev)) {
		/*
		* The requests are supposed to be kept in order. However,
		* we need to be wary in case the timeline->last_request
		* is used as a barrier for external modification to this
		* context.
		*/
		GEM_BUG_ON(prev->context == rq->context &&
		i915_seqno_passed(prev->fence.seqno,
		rq->fence.seqno));

		if (is_power_of_2(prev->engine->mask \| rq->engine->mask))
		i915_sw_fence_await_sw_fence(&rq->submit,
		&prev->submit,