Commit 1e989603 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

ARM: dts: imx6: Move nodes which have no reg property out of bus 



Move tempmon, ldb and pmu nodes from soc node to root node.

The nodes that have been moved do not have any register properties and thus
shouldn't be placed on the bus.

This fixes the following build warnings with W=1:

arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/tempmon missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/ldb missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/pmu missing or empty reg/ranges property

Based on a patch from Simon Horman for r8a7795.dtsi.

Signed-off-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 5b232744

arch/arm/boot/dts/imx6qdl.dtsi

+69 −67
Original line number Diff line number Diff line
@@ -80,6 +80,75 @@ 
		};

	};



	tempmon: tempmon {

		compatible = "fsl,imx6q-tempmon";

		interrupt-parent = <&gpc>;

		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

		fsl,tempmon = <&anatop>;

		fsl,tempmon-data = <&ocotp>;

		clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

	};



	ldb: ldb {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";

		gpr = <&gpr>;

		status = "disabled";



		lvds-channel@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

			status = "disabled";



			port@0 {

				reg = <0>;



				lvds0_mux_0: endpoint {

					remote-endpoint = <&ipu1_di0_lvds0>;

				};

			};



			port@1 {

				reg = <1>;



				lvds0_mux_1: endpoint {

					remote-endpoint = <&ipu1_di1_lvds0>;

				};

			};

		};



		lvds-channel@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;

			status = "disabled";



			port@0 {

				reg = <0>;



				lvds1_mux_0: endpoint {

					remote-endpoint = <&ipu1_di0_lvds1>;

				};

			};



			port@1 {

				reg = <1>;



				lvds1_mux_1: endpoint {

					remote-endpoint = <&ipu1_di1_lvds1>;

				};

			};

		};

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&gpc>;

		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;
@@ -224,11 +293,6 @@ 
			status = "disabled";

		};



		pmu {

			compatible = "arm,cortex-a9-pmu";

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

		};



		aips-bus@2000000 { /* AIPS1 */

			compatible = "fsl,aips-bus", "simple-bus";

			#address-cells = <1>;
@@ -729,14 +793,6 @@ 
				};

			};



			tempmon: tempmon {

				compatible = "fsl,imx6q-tempmon";

				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

				fsl,tempmon = <&anatop>;

				fsl,tempmon-data = <&ocotp>;

				clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

			};



			usbphy1: usbphy@20c9000 {

				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";

				reg = <0x020c9000 0x1000>;
@@ -845,60 +901,6 @@ 
				reg = <0x20e0000 0x4000>;

			};



			ldb: ldb {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";

				gpr = <&gpr>;

				status = "disabled";



				lvds-channel@0 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <0>;

					status = "disabled";



					port@0 {

						reg = <0>;



						lvds0_mux_0: endpoint {

							remote-endpoint = <&ipu1_di0_lvds0>;

						};

					};



					port@1 {

						reg = <1>;



						lvds0_mux_1: endpoint {

							remote-endpoint = <&ipu1_di1_lvds0>;

						};

					};

				};



				lvds-channel@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;

					status = "disabled";



					port@0 {

						reg = <0>;



						lvds1_mux_0: endpoint {

							remote-endpoint = <&ipu1_di0_lvds1>;

						};

					};



					port@1 {

						reg = <1>;



						lvds1_mux_1: endpoint {

							remote-endpoint = <&ipu1_di1_lvds1>;

						};

					};

				};

			};



			dcic1: dcic@20e4000 {

				reg = <0x020e4000 0x4000>;

				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/imx6sl.dtsi

+15 −13
Original line number Diff line number Diff line
@@ -102,6 +102,21 @@ 
		};

	};



	tempmon: tempmon {

		compatible = "fsl,imx6q-tempmon";

		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gpc>;

		fsl,tempmon = <&anatop>;

		fsl,tempmon-data = <&ocotp>;

		clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&gpc>;

		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;
@@ -125,11 +140,6 @@ 
			arm,data-latency = <4 2 3>;

		};



		pmu {

			compatible = "arm,cortex-a9-pmu";

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

		};



		aips1: aips-bus@2000000 {

			compatible = "fsl,aips-bus", "simple-bus";

			#address-cells = <1>;
@@ -615,14 +625,6 @@ 
				};

			};



			tempmon: tempmon {

				compatible = "fsl,imx6q-tempmon";

				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

				fsl,tempmon = <&anatop>;

				fsl,tempmon-data = <&ocotp>;

				clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;

			};



			usbphy1: usbphy@20c9000 {

				compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";

				reg = <0x020c9000 0x1000>;

arch/arm/boot/dts/imx6sx.dtsi

+16 −14
Original line number Diff line number Diff line
@@ -141,18 +141,29 @@ 
		};

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

	tempmon: tempmon {

		compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";

		interrupt-parent = <&gpc>;

		ranges;

		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

		fsl,tempmon = <&anatop>;

		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

		nvmem-cell-names = "calib", "temp_grade";

		clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&gpc>;

		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		interrupt-parent = <&gpc>;

		ranges;



		ocram: sram@900000 {

			compatible = "mmio-sram";

			reg = <0x00900000 0x20000>;
@@ -671,15 +682,6 @@ 
				};

			};



			tempmon: tempmon {

				compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";

				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

				fsl,tempmon = <&anatop>;

				nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

				nvmem-cell-names = "calib", "temp_grade";

				clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;

			};



			usbphy1: usbphy@20c9000 {

				compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";

				reg = <0x020c9000 0x1000>;

arch/arm/boot/dts/imx6ul.dtsi

+17 −15
Original line number Diff line number Diff line
@@ -136,19 +136,30 @@ 
		clock-output-names = "ipp_di1";

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

	tempmon: tempmon {

		compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";

		interrupt-parent = <&gpc>;

		ranges;

		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

		fsl,tempmon = <&anatop>;

		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

		nvmem-cell-names = "calib", "temp_grade";

		clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;

	};



	pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupt-parent = <&gpc>;

		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		interrupt-parent = <&gpc>;

		ranges;



		ocram: sram@900000 {

			compatible = "mmio-sram";

			reg = <0x00900000 0x20000>;
@@ -599,15 +610,6 @@ 
				fsl,anatop = <&anatop>;

			};



			tempmon: tempmon {

				compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";

				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

				fsl,tempmon = <&anatop>;

				nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

				nvmem-cell-names = "calib", "temp_grade";

				clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;

			};



			snvs: snvs@20cc000 {

				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";

				reg = <0x020cc000 0x4000>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE