Commit 1e7445dc authored by Jake Wang's avatar Jake Wang Committed by Alex Deucher
Browse files

drm/amd/display: updated wm table for Renoir 



[Why]
For certain timings, Renoir may underflow due to sr exit  latency
being too slow.

[How]
Updated wm table for renoir.

Signed-off-by: default avatarJake Wang <haonan.wang2@amd.com>
Acked-by: default avatarBindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 73d48f08

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+8 −8
Original line number Diff line number Diff line
@@ -731,32 +731,32 @@ static struct wm_table ddr4_wm_table_rn = { 
			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 9.09,

			.sr_enter_plus_exit_time_us = 10.14,

			.sr_exit_time_us = 11.90,

			.sr_enter_plus_exit_time_us = 12.80,

			.valid = true,

		},

		{

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 11.12,

			.sr_enter_plus_exit_time_us = 12.48,

			.sr_exit_time_us = 13.18,

			.sr_enter_plus_exit_time_us = 14.30,

			.valid = true,

		},

		{

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 11.12,

			.sr_enter_plus_exit_time_us = 12.48,

			.sr_exit_time_us = 13.18,

			.sr_enter_plus_exit_time_us = 14.30,

			.valid = true,

		},

		{

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 11.12,

			.sr_enter_plus_exit_time_us = 12.48,

			.sr_exit_time_us = 13.18,

			.sr_enter_plus_exit_time_us = 14.30,

			.valid = true,

		},

	}

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