gma500: Add the Oaktrail HDMI support (1e585b52) · Commits · 戴 / test

drivers/staging/gma500/Makefile

+3 −1

Original line number	Diff line number	Diff line
		@@ -32,7 +32,9 @@ psb_gfx-$(CONFIG_DRM_PSB_CDV) += cdv_device.o \

		psb_gfx-$(CONFIG_DRM_PSB_MRST) += mrst_device.o \
		mrst_crtc.o \
		mrst_lvds.o
		mrst_lvds.o \
		mrst_hdmi.o \
		mrst_hdmi_i2c.o

		psb_gfx-$(CONFIG_DRM_PSB_MFLD) += mdfld_device.o \
		mdfld_output.o \

drivers/staging/gma500/mrst.h

+35 −0

Original line number	Diff line number	Diff line
		@@ -215,3 +215,38 @@ struct mrst_gct_data {

		#define GCT_R10_HEADER_SIZE 16
		#define GCT_R10_DISPLAY_DESC_SIZE 28

		/*
		* Moorestown HDMI interfaces
		*/

		struct mrst_hdmi_dev {
		struct pci_dev *dev;
		void __iomem *regs;
		unsigned int mmio, mmio_len;
		int dpms_mode;
		struct hdmi_i2c_dev *i2c_dev;

		/* register state */
		u32 saveDPLL_CTRL;
		u32 saveDPLL_DIV_CTRL;
		u32 saveDPLL_ADJUST;
		u32 saveDPLL_UPDATE;
		u32 saveDPLL_CLK_ENABLE;
		u32 savePCH_HTOTAL_B;
		u32 savePCH_HBLANK_B;
		u32 savePCH_HSYNC_B;
		u32 savePCH_VTOTAL_B;
		u32 savePCH_VBLANK_B;
		u32 savePCH_VSYNC_B;
		u32 savePCH_PIPEBCONF;
		u32 savePCH_PIPEBSRC;
		};

		extern void mrst_hdmi_setup(struct drm_device *dev);
		extern void mrst_hdmi_teardown(struct drm_device *dev);
		extern int mrst_hdmi_i2c_init(struct pci_dev *dev);
		extern void mrst_hdmi_i2c_exit(struct pci_dev *dev);
		extern void mrst_hdmi_save(struct drm_device *dev);
		extern void mrst_hdmi_restore(struct drm_device *dev);
		extern void mrst_hdmi_init(struct drm_device dev, struct psb_intel_mode_device mode_dev);

drivers/staging/gma500/mrst_device.c

+178 −68

Original line number	Diff line number	Diff line
		@@ -38,12 +38,13 @@ static const struct psb_ops oaktrail_chip_ops;
		static int mrst_output_init(struct drm_device *dev)
		{
		struct drm_psb_private *dev_priv = dev->dev_private;
		if (dev_priv->iLVDS_enable) {
		if (dev_priv->iLVDS_enable)
		mrst_lvds_init(dev, &dev_priv->mode_dev);
		return 0;
		}
		else
		dev_err(dev->dev, "DSI is not supported\n");
		return -ENODEV;
		if (dev_priv->hdmi_priv)
		mrst_hdmi_init(dev, &dev_priv->mode_dev);
		return 0;
		}

		/*
		@@ -195,8 +196,8 @@ static void mrst_init_pm(struct drm_device *dev)
		static int mrst_save_display_registers(struct drm_device *dev)
		{
		struct drm_psb_private *dev_priv = dev->dev_private;
		struct drm_crtc *crtc;
		struct drm_connector *connector;
		int i;
		u32 pp_stat;

		/* Display arbitration control + watermarks */
		dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
		@@ -208,17 +209,91 @@ static int mrst_save_display_registers(struct drm_device *dev)
		dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
		dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);

		/* Save crtc and output state */
		mutex_lock(&dev->mode_config.mutex);
		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (drm_helper_crtc_in_use(crtc))
		crtc->funcs->save(crtc);
		}
		/* Pipe & plane A info */
		dev_priv->savePIPEACONF = PSB_RVDC32(PIPEACONF);
		dev_priv->savePIPEASRC = PSB_RVDC32(PIPEASRC);
		dev_priv->saveFPA0 = PSB_RVDC32(MRST_FPA0);
		dev_priv->saveFPA1 = PSB_RVDC32(MRST_FPA1);
		dev_priv->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A);
		dev_priv->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A);
		dev_priv->saveHBLANK_A = PSB_RVDC32(HBLANK_A);
		dev_priv->saveHSYNC_A = PSB_RVDC32(HSYNC_A);
		dev_priv->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A);
		dev_priv->saveVBLANK_A = PSB_RVDC32(VBLANK_A);
		dev_priv->saveVSYNC_A = PSB_RVDC32(VSYNC_A);
		dev_priv->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
		dev_priv->saveDSPACNTR = PSB_RVDC32(DSPACNTR);
		dev_priv->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE);
		dev_priv->saveDSPAADDR = PSB_RVDC32(DSPABASE);
		dev_priv->saveDSPASURF = PSB_RVDC32(DSPASURF);
		dev_priv->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF);
		dev_priv->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF);

		/* Save cursor regs */
		dev_priv->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
		dev_priv->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
		dev_priv->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);

		/* Save palette (gamma) */
		for (i = 0; i < 256; i++)
		dev_priv->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2));

		if (dev_priv->hdmi_priv)
		mrst_hdmi_save(dev);

		/* Save performance state */
		dev_priv->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);

		/* LVDS state */
		dev_priv->savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
		dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
		dev_priv->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
		dev_priv->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
		dev_priv->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
		dev_priv->saveLVDS = PSB_RVDC32(LVDS);
		dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
		dev_priv->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
		dev_priv->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
		dev_priv->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);

		/* HW overlay */
		dev_priv->saveOV_OVADD = PSB_RVDC32(OV_OVADD);
		dev_priv->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
		dev_priv->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
		dev_priv->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
		dev_priv->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
		dev_priv->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
		dev_priv->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);

		/* DPST registers */
		dev_priv->saveHISTOGRAM_INT_CONTROL_REG = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
		dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
		dev_priv->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);

		list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->save(connector);
		if (dev_priv->iLVDS_enable) {
		/* Shut down the panel */
		PSB_WVDC32(0, PP_CONTROL);

		do {
		pp_stat = PSB_RVDC32(PP_STATUS);
		} while (pp_stat & 0x80000000);

		/* Turn off the plane */
		PSB_WVDC32(0x58000000, DSPACNTR);
		/* Trigger the plane disable */
		PSB_WVDC32(0, DSPASURF);

		mutex_unlock(&dev->mode_config.mutex);
		/* Wait ~4 ticks */
		msleep(4);

		/* Turn off pipe */
		PSB_WVDC32(0x0, PIPEACONF);
		/* Wait ~8 ticks */
		msleep(8);

		/* Turn off PLLs */
		PSB_WVDC32(0, MRST_DPLL_A);
		}
		return 0;
		}

		@@ -231,18 +306,8 @@ static int mrst_save_display_registers(struct drm_device *dev)
		static int mrst_restore_display_registers(struct drm_device *dev)
		{
		struct drm_psb_private *dev_priv = dev->dev_private;
		struct drm_crtc *crtc;
		struct drm_connector *connector;
		int pp_stat;

		if (!dev_priv->iLVDS_enable) {
		#ifdef CONFIG_X86_MRST
		intel_scu_ipc_simple_command(IPC_MSG_PANEL_ON_OFF,
		IPC_CMD_PANEL_ON);
		/* FIXME: can we avoid this delay ? */
		msleep(2000); /* wait 2 seconds */
		#endif
		}
		u32 pp_stat;
		int i;

		/* Display arbitration + watermarks */
		PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
		@@ -254,54 +319,92 @@ static int mrst_restore_display_registers(struct drm_device *dev)
		PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
		PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);

		/make sure VGA plane is off. it initializes to on after reset!/
		/* Make sure VGA plane is off. it initializes to on after reset!*/
		PSB_WVDC32(0x80000000, VGACNTRL);

		mutex_lock(&dev->mode_config.mutex);
		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		if (drm_helper_crtc_in_use(crtc))
		crtc->funcs->restore(crtc);
		/* set the plls */
		PSB_WVDC32(dev_priv->saveFPA0, MRST_FPA0);
		PSB_WVDC32(dev_priv->saveFPA1, MRST_FPA1);

		/* Actually enable it */
		PSB_WVDC32(dev_priv->saveDPLL_A, MRST_DPLL_A);
		DRM_UDELAY(150);

		list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		connector->funcs->restore(connector);
		/* Restore mode */
		PSB_WVDC32(dev_priv->saveHTOTAL_A, HTOTAL_A);
		PSB_WVDC32(dev_priv->saveHBLANK_A, HBLANK_A);
		PSB_WVDC32(dev_priv->saveHSYNC_A, HSYNC_A);
		PSB_WVDC32(dev_priv->saveVTOTAL_A, VTOTAL_A);
		PSB_WVDC32(dev_priv->saveVBLANK_A, VBLANK_A);
		PSB_WVDC32(dev_priv->saveVSYNC_A, VSYNC_A);
		PSB_WVDC32(dev_priv->savePIPEASRC, PIPEASRC);
		PSB_WVDC32(dev_priv->saveBCLRPAT_A, BCLRPAT_A);

		mutex_unlock(&dev->mode_config.mutex);
		/* Restore performance mode*/
		PSB_WVDC32(dev_priv->savePERF_MODE, MRST_PERF_MODE);

		/* Enable the pipe*/
		if (dev_priv->iLVDS_enable)
		PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF);

		/* Set up the plane*/
		PSB_WVDC32(dev_priv->saveDSPALINOFF, DSPALINOFF);
		PSB_WVDC32(dev_priv->saveDSPASTRIDE, DSPASTRIDE);
		PSB_WVDC32(dev_priv->saveDSPATILEOFF, DSPATILEOFF);

		/* Enable the plane */
		PSB_WVDC32(dev_priv->saveDSPACNTR, DSPACNTR);
		PSB_WVDC32(dev_priv->saveDSPASURF, DSPASURF);

		/* Enable Cursor A */
		PSB_WVDC32(dev_priv->saveDSPACURSOR_CTRL, CURACNTR);
		PSB_WVDC32(dev_priv->saveDSPACURSOR_POS, CURAPOS);
		PSB_WVDC32(dev_priv->saveDSPACURSOR_BASE, CURABASE);

		/* Restore palette (gamma) */
		for (i = 0; i < 256; i++)
		PSB_WVDC32(dev_priv->save_palette_a[i], PALETTE_A + (i << 2));

		if (dev_priv->hdmi_priv)
		mrst_hdmi_restore(dev);

		if (dev_priv->iLVDS_enable) {
		/shutdown the panel/
		PSB_WVDC32(0, PP_CONTROL);
		PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
		PSB_WVDC32(dev_priv->saveLVDS, LVDS); /port 61180h/
		PSB_WVDC32(dev_priv->savePFIT_CONTROL, PFIT_CONTROL);
		PSB_WVDC32(dev_priv->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
		PSB_WVDC32(dev_priv->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
		PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL);
		PSB_WVDC32(dev_priv->savePP_ON_DELAYS, LVDSPP_ON);
		PSB_WVDC32(dev_priv->savePP_OFF_DELAYS, LVDSPP_OFF);
		PSB_WVDC32(dev_priv->savePP_DIVISOR, PP_CYCLE);
		PSB_WVDC32(dev_priv->savePP_CONTROL, PP_CONTROL);
		}

		/* Wait for cycle delay */
		do {
		pp_stat = PSB_RVDC32(PP_STATUS);
		} while (pp_stat & 0x80000000);
		} while (pp_stat & 0x08000000);

		/* Turn off the plane */
		PSB_WVDC32(0x58000000, DSPACNTR);
		PSB_WVDC32(0, DSPASURF);/trigger the plane disable/
		/* Wait ~4 ticks */
		msleep(4);
		/* Turn off pipe */
		PSB_WVDC32(0x0, PIPEACONF);
		/* Wait ~8 ticks */
		msleep(8);
		/* Wait for panel power up */
		do {
		pp_stat = PSB_RVDC32(PP_STATUS);
		} while (pp_stat & 0x10000000);

		/* Restore HW overlay */
		PSB_WVDC32(dev_priv->saveOV_OVADD, OV_OVADD);
		PSB_WVDC32(dev_priv->saveOV_OGAMC0, OV_OGAMC0);
		PSB_WVDC32(dev_priv->saveOV_OGAMC1, OV_OGAMC1);
		PSB_WVDC32(dev_priv->saveOV_OGAMC2, OV_OGAMC2);
		PSB_WVDC32(dev_priv->saveOV_OGAMC3, OV_OGAMC3);
		PSB_WVDC32(dev_priv->saveOV_OGAMC4, OV_OGAMC4);
		PSB_WVDC32(dev_priv->saveOV_OGAMC5, OV_OGAMC5);

		/* DPST registers */
		PSB_WVDC32(dev_priv->saveHISTOGRAM_INT_CONTROL_REG, HISTOGRAM_INT_CONTROL);
		PSB_WVDC32(dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG, HISTOGRAM_LOGIC_CONTROL);
		PSB_WVDC32(dev_priv->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);

		/* Turn off PLLs */
		PSB_WVDC32(0, MRST_DPLL_A);
		} else {
		PSB_WVDC32(DPI_SHUT_DOWN, DPI_CONTROL_REG);
		PSB_WVDC32(0x0, PIPEACONF);
		PSB_WVDC32(0x2faf0000, BLC_PWM_CTL);
		while (REG_READ(0x70008) & 0x40000000)
		cpu_relax();
		while ((PSB_RVDC32(GEN_FIFO_STAT_REG) & DPI_FIFO_EMPTY)
		!= DPI_FIFO_EMPTY)
		cpu_relax();
		PSB_WVDC32(0, DEVICE_READY_REG);
		/* Turn off panel power */
		#ifdef CONFIG_X86_MRST /* FIXME: kill define once modular */
		intel_scu_ipc_simple_command(IPC_MSG_PANEL_ON_OFF,
		IPC_CMD_PANEL_OFF);
		#endif
		}
		return 0;
		}

		@@ -364,10 +467,16 @@ static int mrst_chip_setup(struct drm_device *dev)
		return mid_chip_setup(dev);
		#endif
		dev_priv->ops = &oaktrail_chip_ops;
		mrst_hdmi_setup(dev);
		/* Check - may be better to go via BIOS paths ? */
		return mid_chip_setup(dev);
		}

		static void oaktrail_teardown(struct drm_device *dev)
		{
		mrst_hdmi_teardown(dev);
		}

		const struct psb_ops mrst_chip_ops = {
		.name = "Moorestown",
		.accel_2d = 1,
		@@ -400,6 +509,7 @@ static const struct psb_ops oaktrail_chip_ops = {
		.sgx_offset = MRST_SGX_OFFSET,

		.chip_setup = mid_chip_setup,
		.chip_teardown = oaktrail_teardown,
		.crtc_helper = &mrst_helper_funcs,
		.crtc_funcs = &psb_intel_crtc_funcs,

drivers/staging/gma500/mrst_hdmi.c

0 → 100644

+852 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/staging/gma500/mrst_hdmi_i2c.c

0 → 100644

+327 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright © 2010 Intel Corporation
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice (including the next
		* paragraph) shall be included in all copies or substantial portions of the
		* Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		* DEALINGS IN THE SOFTWARE.
		*
		* Authors:
		* Li Peng <peng.li@intel.com>
		*/

		#include <linux/mutex.h>
		#include <linux/pci.h>
		#include <linux/i2c.h>
		#include <linux/interrupt.h>
		#include <linux/delay.h>
		#include "psb_drv.h"

		#define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
		#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))

		#define HDMI_HCR 0x1000
		#define HCR_DETECT_HDP (1 << 6)
		#define HCR_ENABLE_HDCP (1 << 5)
		#define HCR_ENABLE_AUDIO (1 << 2)
		#define HCR_ENABLE_PIXEL (1 << 1)
		#define HCR_ENABLE_TMDS (1 << 0)
		#define HDMI_HICR 0x1004
		#define HDMI_INTR_I2C_ERROR (1 << 4)
		#define HDMI_INTR_I2C_FULL (1 << 3)
		#define HDMI_INTR_I2C_DONE (1 << 2)
		#define HDMI_INTR_HPD (1 << 0)
		#define HDMI_HSR 0x1008
		#define HDMI_HISR 0x100C
		#define HDMI_HI2CRDB0 0x1200
		#define HDMI_HI2CHCR 0x1240
		#define HI2C_HDCP_WRITE (0 << 2)
		#define HI2C_HDCP_RI_READ (1 << 2)
		#define HI2C_HDCP_READ (2 << 2)
		#define HI2C_EDID_READ (3 << 2)
		#define HI2C_READ_CONTINUE (1 << 1)
		#define HI2C_ENABLE_TRANSACTION (1 << 0)

		#define HDMI_ICRH 0x1100
		#define HDMI_HI2CTDR0 0x1244
		#define HDMI_HI2CTDR1 0x1248

		#define I2C_STAT_INIT 0
		#define I2C_READ_DONE 1
		#define I2C_TRANSACTION_DONE 2

		struct hdmi_i2c_dev {
		struct i2c_adapter *adap;
		struct mutex i2c_lock;
		struct completion complete;
		int status;
		struct i2c_msg *msg;
		int buf_offset;
		};

		static void hdmi_i2c_irq_enable(struct mrst_hdmi_dev *hdmi_dev)
		{
		u32 temp;

		temp = HDMI_READ(HDMI_HICR);
		temp \|= (HDMI_INTR_I2C_ERROR \| HDMI_INTR_I2C_FULL \| HDMI_INTR_I2C_DONE);
		HDMI_WRITE(HDMI_HICR, temp);
		HDMI_READ(HDMI_HICR);
		}

		static void hdmi_i2c_irq_disable(struct mrst_hdmi_dev *hdmi_dev)
		{
		HDMI_WRITE(HDMI_HICR, 0x0);
		HDMI_READ(HDMI_HICR);
		}

		static int xfer_read(struct i2c_adapter adap, struct i2c_msg pmsg)
		{
		struct mrst_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
		struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
		u32 temp;

		i2c_dev->status = I2C_STAT_INIT;
		i2c_dev->msg = pmsg;
		i2c_dev->buf_offset = 0;
		INIT_COMPLETION(i2c_dev->complete);

		/* Enable I2C transaction */
		temp = ((pmsg->len) << 20) \| HI2C_EDID_READ \| HI2C_ENABLE_TRANSACTION;
		HDMI_WRITE(HDMI_HI2CHCR, temp);
		HDMI_READ(HDMI_HI2CHCR);

		while (i2c_dev->status != I2C_TRANSACTION_DONE)
		wait_for_completion_interruptible_timeout(&i2c_dev->complete,
		10 * HZ);

		return 0;
		}

		static int xfer_write(struct i2c_adapter adap, struct i2c_msg pmsg)
		{
		/*
		* XXX: i2c write seems isn't useful for EDID probe, don't do anything
		*/
		return 0;
		}

		static int mrst_hdmi_i2c_access(struct i2c_adapter *adap,
		struct i2c_msg *pmsg,
		int num)
		{
		struct mrst_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
		struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
		int i, err = 0;

		mutex_lock(&i2c_dev->i2c_lock);

		/* Enable i2c unit */
		HDMI_WRITE(HDMI_ICRH, 0x00008760);

		/* Enable irq */
		hdmi_i2c_irq_enable(hdmi_dev);
		for (i = 0; i < num; i++) {
		if (pmsg->len && pmsg->buf) {
		if (pmsg->flags & I2C_M_RD)
		err = xfer_read(adap, pmsg);
		else
		err = xfer_write(adap, pmsg);
		}
		pmsg++; /* next message */
		}

		/* Disable irq */
		hdmi_i2c_irq_disable(hdmi_dev);

		mutex_unlock(&i2c_dev->i2c_lock);

		return i;
		}

		static u32 mrst_hdmi_i2c_func(struct i2c_adapter *adapter)
		{
		return I2C_FUNC_I2C \| I2C_FUNC_10BIT_ADDR;
		}

		static const struct i2c_algorithm mrst_hdmi_i2c_algorithm = {
		.master_xfer = mrst_hdmi_i2c_access,
		.functionality = mrst_hdmi_i2c_func,
		};

		static struct i2c_adapter mrst_hdmi_i2c_adapter = {
		.name = "mrst_hdmi_i2c",
		.nr = 3,
		.owner = THIS_MODULE,
		.class = I2C_CLASS_DDC,
		.algo = &mrst_hdmi_i2c_algorithm,
		};

		static void hdmi_i2c_read(struct mrst_hdmi_dev *hdmi_dev)
		{
		struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
		struct i2c_msg *msg = i2c_dev->msg;
		u8 *buf = msg->buf;
		u32 temp;
		int i, offset;

		offset = i2c_dev->buf_offset;
		for (i = 0; i < 0x10; i++) {
		temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4));
		memcpy(buf + (offset + i * 4), &temp, 4);
		}
		i2c_dev->buf_offset += (0x10 * 4);

		/* clearing read buffer full intr */
		temp = HDMI_READ(HDMI_HISR);
		HDMI_WRITE(HDMI_HISR, temp \| HDMI_INTR_I2C_FULL);
		HDMI_READ(HDMI_HISR);

		/* continue read transaction */
		temp = HDMI_READ(HDMI_HI2CHCR);
		HDMI_WRITE(HDMI_HI2CHCR, temp \| HI2C_READ_CONTINUE);
		HDMI_READ(HDMI_HI2CHCR);

		i2c_dev->status = I2C_READ_DONE;
		return;
		}

		static void hdmi_i2c_transaction_done(struct mrst_hdmi_dev *hdmi_dev)
		{
		struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
		u32 temp;

		/* clear transaction done intr */
		temp = HDMI_READ(HDMI_HISR);
		HDMI_WRITE(HDMI_HISR, temp \| HDMI_INTR_I2C_DONE);
		HDMI_READ(HDMI_HISR);


		temp = HDMI_READ(HDMI_HI2CHCR);
		HDMI_WRITE(HDMI_HI2CHCR, temp & ~HI2C_ENABLE_TRANSACTION);
		HDMI_READ(HDMI_HI2CHCR);

		i2c_dev->status = I2C_TRANSACTION_DONE;
		return;
		}

		static irqreturn_t mrst_hdmi_i2c_handler(int this_irq, void *dev)
		{
		struct mrst_hdmi_dev *hdmi_dev = dev;
		struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
		u32 stat;

		stat = HDMI_READ(HDMI_HISR);

		if (stat & HDMI_INTR_HPD) {
		HDMI_WRITE(HDMI_HISR, stat \| HDMI_INTR_HPD);
		HDMI_READ(HDMI_HISR);
		}

		if (stat & HDMI_INTR_I2C_FULL)
		hdmi_i2c_read(hdmi_dev);

		if (stat & HDMI_INTR_I2C_DONE)
		hdmi_i2c_transaction_done(hdmi_dev);

		complete(&i2c_dev->complete);

		return IRQ_HANDLED;
		}

		/*
		* choose alternate function 2 of GPIO pin 52, 53,
		* which is used by HDMI I2C logic
		*/
		static void mrst_hdmi_i2c_gpio_fix(void)
		{
		void *base;
		unsigned int gpio_base = 0xff12c000;
		int gpio_len = 0x1000;
		u32 temp;

		base = ioremap((resource_size_t)gpio_base, gpio_len);
		if (base == NULL) {
		DRM_ERROR("gpio ioremap fail\n");
		return;
		}

		temp = readl(base + 0x44);
		DRM_DEBUG_DRIVER("old gpio val %x\n", temp);
		writel((temp \| 0x00000a00), (base + 0x44));
		temp = readl(base + 0x44);
		DRM_DEBUG_DRIVER("new gpio val %x\n", temp);

		iounmap(base);
		}

		int mrst_hdmi_i2c_init(struct pci_dev *dev)
		{
		struct mrst_hdmi_dev *hdmi_dev;
		struct hdmi_i2c_dev *i2c_dev;
		int ret;

		hdmi_dev = pci_get_drvdata(dev);

		i2c_dev = kzalloc(sizeof(struct hdmi_i2c_dev), GFP_KERNEL);
		if (i2c_dev == NULL) {
		DRM_ERROR("Can't allocate interface\n");
		ret = -ENOMEM;
		goto exit;
		}

		i2c_dev->adap = &mrst_hdmi_i2c_adapter;
		i2c_dev->status = I2C_STAT_INIT;
		init_completion(&i2c_dev->complete);
		mutex_init(&i2c_dev->i2c_lock);
		i2c_set_adapdata(&mrst_hdmi_i2c_adapter, hdmi_dev);
		hdmi_dev->i2c_dev = i2c_dev;

		/* Enable HDMI I2C function on gpio */
		mrst_hdmi_i2c_gpio_fix();

		/* request irq */
		ret = request_irq(dev->irq, mrst_hdmi_i2c_handler, IRQF_SHARED,
		mrst_hdmi_i2c_adapter.name, hdmi_dev);
		if (ret) {
		DRM_ERROR("Failed to request IRQ for I2C controller\n");
		goto err;
		}

		/* Adapter registration */
		ret = i2c_add_numbered_adapter(&mrst_hdmi_i2c_adapter);
		return ret;

		err:
		kfree(i2c_dev);
		exit:
		return ret;
		}

		void mrst_hdmi_i2c_exit(struct pci_dev *dev)
		{
		struct mrst_hdmi_dev *hdmi_dev;
		struct hdmi_i2c_dev *i2c_dev;

		hdmi_dev = pci_get_drvdata(dev);
		if (i2c_del_adapter(&mrst_hdmi_i2c_adapter))
		DRM_DEBUG_DRIVER("Failed to delete hdmi-i2c adapter\n");

		i2c_dev = hdmi_dev->i2c_dev;
		kfree(i2c_dev);
		free_irq(dev->irq, hdmi_dev);
		}

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