Commit 1e2da4ad authored by Brian Norris's avatar Brian Norris
Browse files

Merge tag 'for-4.9' of github.com:linux-nand/linux 



"
Notable core changes:
- add the infrastructure to automate NAND timings configuration
- provide a generic DT property to maximize ECC strength

The rest is just a bunch of minor drivers and core fixes/cleanup
patches.
"

Also not noted: some refactoring in the core bad block table handling,
to help with improving some of the logic in error cases.

Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parents 5e149073 d44154f9

Documentation/devicetree/bindings/mtd/nand.txt

+9 −0
Original line number Diff line number Diff line
@@ -35,6 +35,15 @@ Optional NAND chip properties: 
- nand-ecc-step-size: integer representing the number of data bytes

		      that are covered by a single ECC step.



- nand-ecc-maximize: boolean used to specify that you want to maximize ECC

		     strength. The maximum ECC strength is both controller and

		     chip dependent. The controller side has to select the ECC

		     config providing the best strength and taking the OOB area

		     size constraint into account.

		     This is particularly useful when only the in-band area is

		     used by the upper layers, and you want to make your NAND

		     as reliable as possible.



The ECC strength and ECC step size properties define the correction capability

of a controller. Together, they say a controller can correct "{strength} bit

errors per {size} bytes".

MAINTAINERS

+6 −0
Original line number Diff line number Diff line
@@ -5976,6 +5976,12 @@ M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> 
S:	Maintained

F:	drivers/dma/dma-jz4780.c



INGENIC JZ4780 NAND DRIVER

M:	Harvey Hunt <harveyhuntnexus@gmail.com>

L:	linux-mtd@lists.infradead.org

S:	Maintained

F:	drivers/mtd/nand/jz4780_*



INTEGRITY MEASUREMENT ARCHITECTURE (IMA)

M:	Mimi Zohar <zohar@linux.vnet.ibm.com>

M:	Dmitry Kasatkin <dmitry.kasatkin@gmail.com>

drivers/mtd/nand/Kconfig

+6 −6
Original line number Diff line number Diff line
@@ -88,11 +88,11 @@ config MTD_NAND_AMS_DELTA 
	  Support for NAND flash on Amstrad E3 (Delta).



config MTD_NAND_OMAP2

	tristate "NAND Flash device on OMAP2, OMAP3 and OMAP4"

	depends on ARCH_OMAP2PLUS

	tristate "NAND Flash device on OMAP2, OMAP3, OMAP4 and Keystone"

	depends on (ARCH_OMAP2PLUS || ARCH_KEYSTONE)

	help

          Support for NAND flash on Texas Instruments OMAP2, OMAP3 and OMAP4

	  platforms.

          Support for NAND flash on Texas Instruments OMAP2, OMAP3, OMAP4

	  and Keystone platforms.



config MTD_NAND_OMAP_BCH

	depends on MTD_NAND_OMAP2
@@ -428,7 +428,7 @@ config MTD_NAND_ORION 


config MTD_NAND_FSL_ELBC

	tristate "NAND support for Freescale eLBC controllers"

	depends on PPC

	depends on FSL_SOC

	select FSL_LBC

	help

	  Various Freescale chips, including the 8313, include a NAND Flash
@@ -438,7 +438,7 @@ config MTD_NAND_FSL_ELBC 


config MTD_NAND_FSL_IFC

	tristate "NAND support for Freescale IFC controller"

	depends on MTD_NAND && (FSL_SOC || ARCH_LAYERSCAPE)

	depends on FSL_SOC || ARCH_LAYERSCAPE

	select FSL_IFC

	select MEMORY

	help

drivers/mtd/nand/bf5xx_nand.c

+1 −2
Original line number Diff line number Diff line
@@ -761,8 +761,7 @@ static int bf5xx_nand_probe(struct platform_device *pdev) 


	platform_set_drvdata(pdev, info);



	spin_lock_init(&info->controller.lock);

	init_waitqueue_head(&info->controller.wq);

	nand_hw_control_init(&info->controller);



	info->device     = &pdev->dev;

	info->platform   = plat;

drivers/mtd/nand/brcmnand/brcmnand.c

+7 −8
Original line number Diff line number Diff line
@@ -1336,7 +1336,7 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, 
		u32 *flash_cache = (u32 *)ctrl->flash_cache;

		int i;



		brcmnand_soc_data_bus_prepare(ctrl->soc);

		brcmnand_soc_data_bus_prepare(ctrl->soc, true);



		/*

		 * Must cache the FLASH_CACHE now, since changes in
@@ -1349,7 +1349,7 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, 
			 */

			flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));



		brcmnand_soc_data_bus_unprepare(ctrl->soc);

		brcmnand_soc_data_bus_unprepare(ctrl->soc, true);



		/* Cleanup from HW quirk: restore SECTOR_SIZE_1K */

		if (host->hwcfg.sector_size_1k)
@@ -1565,12 +1565,12 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, 
		brcmnand_waitfunc(mtd, chip);



		if (likely(buf)) {

			brcmnand_soc_data_bus_prepare(ctrl->soc);

			brcmnand_soc_data_bus_prepare(ctrl->soc, false);



			for (j = 0; j < FC_WORDS; j++, buf++)

				*buf = brcmnand_read_fc(ctrl, j);



			brcmnand_soc_data_bus_unprepare(ctrl->soc);

			brcmnand_soc_data_bus_unprepare(ctrl->soc, false);

		}



		if (oob)
@@ -1815,12 +1815,12 @@ static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, 
		(void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);



		if (buf) {

			brcmnand_soc_data_bus_prepare(ctrl->soc);

			brcmnand_soc_data_bus_prepare(ctrl->soc, false);



			for (j = 0; j < FC_WORDS; j++, buf++)

				brcmnand_write_fc(ctrl, j, *buf);



			brcmnand_soc_data_bus_unprepare(ctrl->soc);

			brcmnand_soc_data_bus_unprepare(ctrl->soc, false);

		} else if (oob) {

			for (j = 0; j < FC_WORDS; j++)

				brcmnand_write_fc(ctrl, j, 0xffffffff);
@@ -2370,8 +2370,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) 


	init_completion(&ctrl->done);

	init_completion(&ctrl->dma_done);

	spin_lock_init(&ctrl->controller.lock);

	init_waitqueue_head(&ctrl->controller.wq);

	nand_hw_control_init(&ctrl->controller);

	INIT_LIST_HEAD(&ctrl->host_list);



	/* NAND register range */

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