Commit 1e18ac7a authored Jul 09, 2015 by Paul Burton Committed by Ralf Baechle Jul 10, 2015

MIPS: c-r4k: Extend way_string array



The L2 cache in the I6400 core has 16 ways, so extend the way_string
array to take such caches into account.

[ralf@linux-mips.org: Other already supported CPUs are free to support
more than 8 ways of cache as well.]

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10640/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 6b5e741e

arch/mips/mm/c-r4k.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -945,7 +945,9 @@ static void b5k_instruction_hazard(void)
		}

		static char *way_string[] = { NULL, "direct mapped", "2-way",
		"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
		"3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
		"9-way", "10-way", "11-way", "12-way",
		"13-way", "14-way", "15-way", "16-way",
		};

		static void probe_pcache(void)

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