Merge branch 'for-next/perf' into aarch64/for-next/core

* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)

ARMv8.2 introduces the optional Statistical Profiling Extension for collecting

performance sample data using an in-memory trace buffer.

** SPE Required properties:

- compatible : should be one of:

	       "arm,statistical-profiling-extension-v1"

- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where

               SPE is only supported on a subset of the CPUs, please consult

	       the arm,gic-v3 binding for details on describing a PPI partition.

** Example:

spe-pmu {

        compatible = "arm,statistical-profiling-extension-v1";

        interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>;

};

HiSilicon SoC uncore Performance Monitoring Unit (PMU)

======================================================

The HiSilicon SoC chip includes various independent system device PMUs

such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are

independent and have hardware logic to gather statistics and performance

information.

The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster

(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is

called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has

two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.

HiSilicon SoC uncore PMU driver

---------------------------------------

Each device PMU has separate registers for event counting, control and

interrupt, and the PMU driver shall register perf PMU drivers like L3C,

HHA and DDRC etc. The available events and configuration options shall

be described in the sysfs, see :

/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or

/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.

The "perf list" command shall list the available events from sysfs.

Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU

name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.

where "sccl-id" is the identifier of the SCCL and "index-id" is the index of

module.

e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in

SCCL ID #3.

e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in

SCCL ID #1.

The driver also provides a "cpumask" sysfs attribute, which shows the CPU core

ID used to count the uncore PMU event.

Example usage of perf:

$# perf list

hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]

------------------------------------------

hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]

------------------------------------------

hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]

------------------------------------------

hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]

------------------------------------------

$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5

$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5

The current driver does not support sampling. So "perf record" is unsupported.

Also attach to a task is unsupported as the events are all uncore.

Note: Please contact the maintainer for a complete list of events supported for

the PMU devices in the SoC and its information if needed.

F:	drivers/net/ethernet/hisilicon/

F:	Documentation/devicetree/bindings/net/hisilicon*.txt

HISILICON PMU DRIVER

M:	Shaokun Zhang <zhangshaokun@hisilicon.com>

W:	http://www.hisilicon.com

S:	Supported

F:	drivers/perf/hisilicon

F:	Documentation/perf/hisi-pmu.txt

HISILICON ROCE DRIVER

M:	Lijun Ou <oulijun@huawei.com>

M:	Wei Hu(Xavier) <xavier.huwei@huawei.com>

#define dmb(opt)	asm volatile("dmb " #opt : : : "memory")

#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")

#define psb_csync()	asm volatile("hint #17" : : : "memory")

#define mb()		dsb(sy)

#define rmb()		dsb(ld)

#define wmb()		dsb(st)

#define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)

#define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)

/*** Statistical Profiling Extension ***/

/* ID registers */

#define SYS_PMSIDR_EL1			sys_reg(3, 0, 9, 9, 7)

#define SYS_PMSIDR_EL1_FE_SHIFT		0

#define SYS_PMSIDR_EL1_FT_SHIFT		1

#define SYS_PMSIDR_EL1_FL_SHIFT		2

#define SYS_PMSIDR_EL1_ARCHINST_SHIFT	3

#define SYS_PMSIDR_EL1_LDS_SHIFT	4

#define SYS_PMSIDR_EL1_ERND_SHIFT	5

#define SYS_PMSIDR_EL1_INTERVAL_SHIFT	8

#define SYS_PMSIDR_EL1_INTERVAL_MASK	0xfUL

#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12

#define SYS_PMSIDR_EL1_MAXSIZE_MASK	0xfUL

#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT	16

#define SYS_PMSIDR_EL1_COUNTSIZE_MASK	0xfUL

#define SYS_PMBIDR_EL1			sys_reg(3, 0, 9, 10, 7)

#define SYS_PMBIDR_EL1_ALIGN_SHIFT	0

#define SYS_PMBIDR_EL1_ALIGN_MASK	0xfU

#define SYS_PMBIDR_EL1_P_SHIFT		4

#define SYS_PMBIDR_EL1_F_SHIFT		5

/* Sampling controls */

#define SYS_PMSCR_EL1			sys_reg(3, 0, 9, 9, 0)

#define SYS_PMSCR_EL1_E0SPE_SHIFT	0

#define SYS_PMSCR_EL1_E1SPE_SHIFT	1

#define SYS_PMSCR_EL1_CX_SHIFT		3

#define SYS_PMSCR_EL1_PA_SHIFT		4

#define SYS_PMSCR_EL1_TS_SHIFT		5

#define SYS_PMSCR_EL1_PCT_SHIFT		6

#define SYS_PMSCR_EL2			sys_reg(3, 4, 9, 9, 0)

#define SYS_PMSCR_EL2_E0HSPE_SHIFT	0

#define SYS_PMSCR_EL2_E2SPE_SHIFT	1

#define SYS_PMSCR_EL2_CX_SHIFT		3

#define SYS_PMSCR_EL2_PA_SHIFT		4

#define SYS_PMSCR_EL2_TS_SHIFT		5

#define SYS_PMSCR_EL2_PCT_SHIFT		6

#define SYS_PMSICR_EL1			sys_reg(3, 0, 9, 9, 2)

#define SYS_PMSIRR_EL1			sys_reg(3, 0, 9, 9, 3)

#define SYS_PMSIRR_EL1_RND_SHIFT	0

#define SYS_PMSIRR_EL1_INTERVAL_SHIFT	8

#define SYS_PMSIRR_EL1_INTERVAL_MASK	0xffffffUL

/* Filtering controls */

#define SYS_PMSFCR_EL1			sys_reg(3, 0, 9, 9, 4)

#define SYS_PMSFCR_EL1_FE_SHIFT		0

#define SYS_PMSFCR_EL1_FT_SHIFT		1

#define SYS_PMSFCR_EL1_FL_SHIFT		2

#define SYS_PMSFCR_EL1_B_SHIFT		16

#define SYS_PMSFCR_EL1_LD_SHIFT		17

#define SYS_PMSFCR_EL1_ST_SHIFT		18

#define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)

#define SYS_PMSEVFR_EL1_RES0		0x0000ffff00ff0f55UL

#define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)

#define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0

/* Buffer controls */

#define SYS_PMBLIMITR_EL1		sys_reg(3, 0, 9, 10, 0)

#define SYS_PMBLIMITR_EL1_E_SHIFT	0

#define SYS_PMBLIMITR_EL1_FM_SHIFT	1

#define SYS_PMBLIMITR_EL1_FM_MASK	0x3UL

#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ	(0 << SYS_PMBLIMITR_EL1_FM_SHIFT)

#define SYS_PMBPTR_EL1			sys_reg(3, 0, 9, 10, 1)

/* Buffer error reporting */

#define SYS_PMBSR_EL1			sys_reg(3, 0, 9, 10, 3)

#define SYS_PMBSR_EL1_COLL_SHIFT	16

#define SYS_PMBSR_EL1_S_SHIFT		17

#define SYS_PMBSR_EL1_EA_SHIFT		18

#define SYS_PMBSR_EL1_DL_SHIFT		19

#define SYS_PMBSR_EL1_EC_SHIFT		26

#define SYS_PMBSR_EL1_EC_MASK		0x3fUL

#define SYS_PMBSR_EL1_EC_BUF		(0x0UL << SYS_PMBSR_EL1_EC_SHIFT)

#define SYS_PMBSR_EL1_EC_FAULT_S1	(0x24UL << SYS_PMBSR_EL1_EC_SHIFT)

#define SYS_PMBSR_EL1_EC_FAULT_S2	(0x25UL << SYS_PMBSR_EL1_EC_SHIFT)

#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT	0

#define SYS_PMBSR_EL1_FAULT_FSC_MASK	0x3fUL

#define SYS_PMBSR_EL1_BUF_BSC_SHIFT	0

#define SYS_PMBSR_EL1_BUF_BSC_MASK	0x3fUL

#define SYS_PMBSR_EL1_BUF_BSC_FULL	(0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)

/*** End of Statistical Profiling Extension ***/

#define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)

#define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)