Commit 1e02ce4c authored by Andy Lutomirski's avatar Andy Lutomirski Committed by Ingo Molnar
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x86: Store a per-cpu shadow copy of CR4 



Context switches and TLB flushes can change individual bits of CR4.
CR4 reads take several cycles, so store a shadow copy of CR4 in a
per-cpu variable.

To avoid wasting a cache line, I added the CR4 shadow to
cpu_tlbstate, which is already touched in switch_mm.  The heaviest
users of the cr4 shadow will be switch_mm and __switch_to_xtra, and
__switch_to_xtra is called shortly after switch_mm during context
switch, so the cacheline is likely to be hot.

Signed-off-by: default avatarAndy Lutomirski <luto@amacapital.net>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Vince Weaver <vince@deater.net>
Cc: "hillf.zj" <hillf.zj@alibaba-inc.com>
Cc: Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: http://lkml.kernel.org/r/3a54dd3353fffbf84804398e00dfdc5b7c1afd7d.1414190806.git.luto@amacapital.net


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 375074cc

arch/x86/include/asm/paravirt.h

+3 −3
Original line number Diff line number Diff line
@@ -80,16 +80,16 @@ static inline void write_cr3(unsigned long x) 
	PVOP_VCALL1(pv_mmu_ops.write_cr3, x);

}



static inline unsigned long read_cr4(void)

static inline unsigned long __read_cr4(void)

{

	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);

}

static inline unsigned long read_cr4_safe(void)

static inline unsigned long __read_cr4_safe(void)

{

	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);

}



static inline void write_cr4(unsigned long x)

static inline void __write_cr4(unsigned long x)

{

	PVOP_VCALL1(pv_cpu_ops.write_cr4, x);

}

arch/x86/include/asm/special_insns.h

+3 −3
Original line number Diff line number Diff line
@@ -137,17 +137,17 @@ static inline void write_cr3(unsigned long x) 
	native_write_cr3(x);

}



static inline unsigned long read_cr4(void)

static inline unsigned long __read_cr4(void)

{

	return native_read_cr4();

}



static inline unsigned long read_cr4_safe(void)

static inline unsigned long __read_cr4_safe(void)

{

	return native_read_cr4_safe();

}



static inline void write_cr4(unsigned long x)

static inline void __write_cr4(unsigned long x)

{

	native_write_cr4(x);

}

arch/x86/include/asm/tlbflush.h

+39 −13
Original line number Diff line number Diff line
@@ -15,14 +15,37 @@ 
#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)

#endif



struct tlb_state {

#ifdef CONFIG_SMP

	struct mm_struct *active_mm;

	int state;

#endif



	/*

	 * Access to this CR4 shadow and to H/W CR4 is protected by

	 * disabling interrupts when modifying either one.

	 */

	unsigned long cr4;

};

DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);



/* Initialize cr4 shadow for this CPU. */

static inline void cr4_init_shadow(void)

{

	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());

}



/* Set in this cpu's CR4. */

static inline void cr4_set_bits(unsigned long mask)

{

	unsigned long cr4;



	cr4 = read_cr4();

	cr4 = this_cpu_read(cpu_tlbstate.cr4);

	if ((cr4 | mask) != cr4) {

		cr4 |= mask;

	write_cr4(cr4);

		this_cpu_write(cpu_tlbstate.cr4, cr4);

		__write_cr4(cr4);

	}

}



/* Clear in this cpu's CR4. */
@@ -30,9 +53,18 @@ static inline void cr4_clear_bits(unsigned long mask) 
{

	unsigned long cr4;



	cr4 = read_cr4();

	cr4 = this_cpu_read(cpu_tlbstate.cr4);

	if ((cr4 & ~mask) != cr4) {

		cr4 &= ~mask;

	write_cr4(cr4);

		this_cpu_write(cpu_tlbstate.cr4, cr4);

		__write_cr4(cr4);

	}

}



/* Read the CR4 shadow. */

static inline unsigned long cr4_read_shadow(void)

{

	return this_cpu_read(cpu_tlbstate.cr4);

}



/*
@@ -61,7 +93,7 @@ static inline void __native_flush_tlb_global_irq_disabled(void) 
{

	unsigned long cr4;



	cr4 = native_read_cr4();

	cr4 = this_cpu_read(cpu_tlbstate.cr4);

	/* clear PGE */

	native_write_cr4(cr4 & ~X86_CR4_PGE);

	/* write old PGE again and flush TLBs */
@@ -221,12 +253,6 @@ void native_flush_tlb_others(const struct cpumask *cpumask, 
#define TLBSTATE_OK	1

#define TLBSTATE_LAZY	2



struct tlb_state {

	struct mm_struct *active_mm;

	int state;

};

DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);



static inline void reset_lazy_tlbstate(void)

{

	this_cpu_write(cpu_tlbstate.state, 0);

arch/x86/include/asm/virtext.h

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ static inline void cpu_vmxoff(void) 


static inline int cpu_vmx_enabled(void)

{

	return read_cr4() & X86_CR4_VMXE;

	return __read_cr4() & X86_CR4_VMXE;

}



/** Disable VMX if it is enabled on the current CPU

arch/x86/kernel/acpi/sleep.c

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ int x86_acpi_suspend_lowlevel(void) 


	header->pmode_cr0 = read_cr0();

	if (__this_cpu_read(cpu_info.cpuid_level) >= 0) {

		header->pmode_cr4 = read_cr4();

		header->pmode_cr4 = __read_cr4();

		header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_CR4);

	}

	if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,

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