drm/amd/display: Do not disable pipe split if mode is not supported (1dfedb39) · Commits · 戴 / test

[WHY] If mode is not supported, pipe split should not be disabled. This may cause more modes to fail. [HOW] Check for mode support before disabling pipe split. This commit was previously reverted as it was thought to have problems, but those issues have been resolved. Signed-off-by:

Sung Lee <sung.lee@amd.com> Reviewed-by:

Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:

Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -2623,19 +2623,24 @@ int dcn20_validate_apply_pipe_split_flags(

		/* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
		if (avoid_split) {
		int max_mpc_comb = context->bw_ctx.dml.vba.maxMpcComb;

		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
		if (!context->res_ctx.pipe_ctx[i].stream)
		continue;

		for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
		if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
		if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1 &&
		context->bw_ctx.dml.vba.ModeSupport[vlevel][0])
		break;
		/* Impossible to not split this pipe */
		if (vlevel > context->bw_ctx.dml.soc.num_states)
		vlevel = vlevel_split;
		else
		max_mpc_comb = 0;
		pipe_idx++;
		}
		context->bw_ctx.dml.vba.maxMpcComb = 0;
		context->bw_ctx.dml.vba.maxMpcComb = max_mpc_comb;
		}

		/* Split loop sets which pipe should be split based on dml outputs and dc flags */

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