clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 (1dfbec39) · Commits · 戴 / test

Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399. But dues to the carelessly copying from RK3036 when the RK3399 bringing up, the refdiv == 6, it will increase the lock time, and it is not an optimal configuration. Let's fix them for the lock time and jitter are lower: 800 MHz: - FVCO == 2.4 GHz, revdiv == 1. 1 GHz: - FVCO == 3 GHz, revdiv == 1. Signed-off-by:

Xing Zheng <zhengxing@rock-chips.com> Signed-off-by:

Heiko Stuebner <heiko@sntech.de>

drivers/clk/rockchip/clk-rk3399.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -77,7 +77,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
		RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
		RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
		RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
		RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
		RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
		RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
		RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
		RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
		@@ -87,7 +87,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
		RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
		RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
		RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
		RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
		RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
		RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
		RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
		RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),

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