Commit 1ddc07d0 authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: Add WM8958 noise gate support 



Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 70ce6aee

include/linux/mfd/wm8994/registers.h

+45 −0
Original line number Diff line number Diff line
@@ -134,6 +134,8 @@ 
#define WM8994_AIF1_DAC1_FILTERS_2              0x421

#define WM8994_AIF1_DAC2_FILTERS_1              0x422

#define WM8994_AIF1_DAC2_FILTERS_2              0x423

#define WM8958_AIF1_DAC1_NOISE_GATE             0x430

#define WM8958_AIF1_DAC2_NOISE_GATE             0x431

#define WM8994_AIF1_DRC1_1                      0x440

#define WM8994_AIF1_DRC1_2                      0x441

#define WM8994_AIF1_DRC1_3                      0x442
@@ -191,6 +193,7 @@ 
#define WM8994_AIF2_ADC_FILTERS                 0x510

#define WM8994_AIF2_DAC_FILTERS_1               0x520

#define WM8994_AIF2_DAC_FILTERS_2               0x521

#define WM8958_AIF2_DAC_NOISE_GATE              0x530

#define WM8994_AIF2_DRC_1                       0x540

#define WM8994_AIF2_DRC_2                       0x541

#define WM8994_AIF2_DRC_3                       0x542
@@ -2987,6 +2990,34 @@ 
#define WM8994_AIF1DAC2_3D_ENA_SHIFT                 8  /* AIF1DAC2_3D_ENA */

#define WM8994_AIF1DAC2_3D_ENA_WIDTH                 1  /* AIF1DAC2_3D_ENA */



/*

 * R1072 (0x430) - AIF1 DAC1 Noise Gate

 */

#define WM8958_AIF1DAC1_NG_HLD_MASK             0x0060  /* AIF1DAC1_NG_HLD - [6:5] */

#define WM8958_AIF1DAC1_NG_HLD_SHIFT                 5  /* AIF1DAC1_NG_HLD - [6:5] */

#define WM8958_AIF1DAC1_NG_HLD_WIDTH                 2  /* AIF1DAC1_NG_HLD - [6:5] */

#define WM8958_AIF1DAC1_NG_THR_MASK             0x000E  /* AIF1DAC1_NG_THR - [3:1] */

#define WM8958_AIF1DAC1_NG_THR_SHIFT                 1  /* AIF1DAC1_NG_THR - [3:1] */

#define WM8958_AIF1DAC1_NG_THR_WIDTH                 3  /* AIF1DAC1_NG_THR - [3:1] */

#define WM8958_AIF1DAC1_NG_ENA                  0x0001  /* AIF1DAC1_NG_ENA */

#define WM8958_AIF1DAC1_NG_ENA_MASK             0x0001  /* AIF1DAC1_NG_ENA */

#define WM8958_AIF1DAC1_NG_ENA_SHIFT                 0  /* AIF1DAC1_NG_ENA */

#define WM8958_AIF1DAC1_NG_ENA_WIDTH                 1  /* AIF1DAC1_NG_ENA */



/*

 * R1073 (0x431) - AIF1 DAC2 Noise Gate

 */

#define WM8958_AIF1DAC2_NG_HLD_MASK             0x0060  /* AIF1DAC2_NG_HLD - [6:5] */

#define WM8958_AIF1DAC2_NG_HLD_SHIFT                 5  /* AIF1DAC2_NG_HLD - [6:5] */

#define WM8958_AIF1DAC2_NG_HLD_WIDTH                 2  /* AIF1DAC2_NG_HLD - [6:5] */

#define WM8958_AIF1DAC2_NG_THR_MASK             0x000E  /* AIF1DAC2_NG_THR - [3:1] */

#define WM8958_AIF1DAC2_NG_THR_SHIFT                 1  /* AIF1DAC2_NG_THR - [3:1] */

#define WM8958_AIF1DAC2_NG_THR_WIDTH                 3  /* AIF1DAC2_NG_THR - [3:1] */

#define WM8958_AIF1DAC2_NG_ENA                  0x0001  /* AIF1DAC2_NG_ENA */

#define WM8958_AIF1DAC2_NG_ENA_MASK             0x0001  /* AIF1DAC2_NG_ENA */

#define WM8958_AIF1DAC2_NG_ENA_SHIFT                 0  /* AIF1DAC2_NG_ENA */

#define WM8958_AIF1DAC2_NG_ENA_WIDTH                 1  /* AIF1DAC2_NG_ENA */



/*

 * R1088 (0x440) - AIF1 DRC1 (1)

 */
@@ -3598,6 +3629,20 @@ 
#define WM8994_AIF2DAC_3D_ENA_SHIFT                  8  /* AIF2DAC_3D_ENA */

#define WM8994_AIF2DAC_3D_ENA_WIDTH                  1  /* AIF2DAC_3D_ENA */



/*

 * R1328 (0x530) - AIF2 DAC Noise Gate

 */

#define WM8958_AIF2DAC_NG_HLD_MASK              0x0060  /* AIF2DAC_NG_HLD - [6:5] */

#define WM8958_AIF2DAC_NG_HLD_SHIFT                  5  /* AIF2DAC_NG_HLD - [6:5] */

#define WM8958_AIF2DAC_NG_HLD_WIDTH                  2  /* AIF2DAC_NG_HLD - [6:5] */

#define WM8958_AIF2DAC_NG_THR_MASK              0x000E  /* AIF2DAC_NG_THR - [3:1] */

#define WM8958_AIF2DAC_NG_THR_SHIFT                  1  /* AIF2DAC_NG_THR - [3:1] */

#define WM8958_AIF2DAC_NG_THR_WIDTH                  3  /* AIF2DAC_NG_THR - [3:1] */

#define WM8958_AIF2DAC_NG_ENA                   0x0001  /* AIF2DAC_NG_ENA */

#define WM8958_AIF2DAC_NG_ENA_MASK              0x0001  /* AIF2DAC_NG_ENA */

#define WM8958_AIF2DAC_NG_ENA_SHIFT                  0  /* AIF2DAC_NG_ENA */

#define WM8958_AIF2DAC_NG_ENA_WIDTH                  1  /* AIF2DAC_NG_ENA */



/*

 * R1344 (0x540) - AIF2 DRC (1)

 */

sound/soc/codecs/wm8994-tables.c

+6 −6
Original line number Diff line number Diff line
@@ -1073,8 +1073,8 @@ const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = { 
	{ 0x0000, 0x0000 }, /* R1069 */

	{ 0x0000, 0x0000 }, /* R1070 */

	{ 0x0000, 0x0000 }, /* R1071 */

	{ 0x0000, 0x0000 }, /* R1072 */

	{ 0x0000, 0x0000 }, /* R1073 */

	{ 0x006F, 0x006F }, /* R1072  - AIF1 DAC1 Noise Gate */

	{ 0x006F, 0x006F }, /* R1073  - AIF1 DAC2 Noise Gate */

	{ 0x0000, 0x0000 }, /* R1074 */

	{ 0x0000, 0x0000 }, /* R1075 */

	{ 0x0000, 0x0000 }, /* R1076 */
@@ -1329,7 +1329,7 @@ const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = { 
	{ 0x0000, 0x0000 }, /* R1325 */

	{ 0x0000, 0x0000 }, /* R1326 */

	{ 0x0000, 0x0000 }, /* R1327 */

	{ 0x0000, 0x0000 }, /* R1328 */

	{ 0x006F, 0x006F }, /* R1328  - AIF2 DAC Noise Gate */

	{ 0x0000, 0x0000 }, /* R1329 */

	{ 0x0000, 0x0000 }, /* R1330 */

	{ 0x0000, 0x0000 }, /* R1331 */
@@ -2646,8 +2646,8 @@ const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = { 
	0x0000,     /* R1069 */

	0x0000,     /* R1070 */

	0x0000,     /* R1071 */

	0x0000,     /* R1072 */

	0x0000,     /* R1073 */

	0x0068,     /* R1072  - AIF1 DAC1 Noise Gate */

	0x0068,     /* R1073  - AIF1 DAC2 Noise Gate */

	0x0000,     /* R1074 */

	0x0000,     /* R1075 */

	0x0000,     /* R1076 */
@@ -2902,7 +2902,7 @@ const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = { 
	0x0000,     /* R1325 */

	0x0000,     /* R1326 */

	0x0000,     /* R1327 */

	0x0000,     /* R1328 */

	0x0068,     /* R1328  - AIF2 DAC Noise Gate */

	0x0000,     /* R1329 */

	0x0000,     /* R1330 */

	0x0000,     /* R1331 */

sound/soc/codecs/wm8994.c

+38 −0
Original line number Diff line number Diff line
@@ -282,6 +282,7 @@ static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 
static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);

static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);

static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);

static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);



#define WM8994_DRC_SWITCH(xname, reg, shift) \

{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
@@ -661,8 +662,45 @@ SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 
	       eq_tlv),

};



static const char *wm8958_ng_text[] = {

	"30ms", "125ms", "250ms", "500ms",

};



static const struct soc_enum wm8958_aif1dac1_ng_hold =

	SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,

			WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);



static const struct soc_enum wm8958_aif1dac2_ng_hold =

	SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,

			WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);



static const struct soc_enum wm8958_aif2dac_ng_hold =

	SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,

			WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);



static const struct snd_kcontrol_new wm8958_snd_controls[] = {

SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),



SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,

	   WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),

SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),

SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",

	       WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,

	       7, 1, ng_tlv),



SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,

	   WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),

SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),

SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",

	       WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,

	       7, 1, ng_tlv),



SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,

	   WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),

SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),

SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",

	       WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,

	       7, 1, ng_tlv),

};



static int clk_sys_event(struct snd_soc_dapm_widget *w,

CRA Git | Maintained and supported by SUSTech CRA and CCSE