Commit 1dbf6a81 authored Feb 03, 2016 by Paul Burton Committed by Ralf Baechle May 13, 2016

MIPS: Add M6250 cases to CPU switch statements

Add casses supporting the M6250 CPU to various switch statements in the
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12374/

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent df8b1a5e

arch/mips/include/asm/cpu-type.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -77,6 +77,10 @@ static inline int __pure __get_cpu_type(const int cpu_type)
		*/
		#endif

		#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R6
		case CPU_M6250:
		#endif

		#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
		case CPU_I6400:
		case CPU_P6600:

arch/mips/mm/c-r4k.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -1286,6 +1286,7 @@ static void probe_pcache(void)
		case CPU_QEMU_GENERIC:
		case CPU_I6400:
		case CPU_P6600:
		case CPU_M6250:
		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
		(c->icache.waysize > PAGE_SIZE))
		c->icache.flags \|= MIPS_CACHE_ALIASES;

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