Commit 1dbcd8d4 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-4.20-rc' of... 

Merge tag 'phy-for-4.20-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-linus

Kishon writes:

phy: for 4.20-rc

 *) Fix updating HSTX_TRIM tuning parameter in qcom-qusb2 PHY driver
 *) Fix inconsistencies between dt-bindings and the driver
 *) Add "Depend on HAS_IOMEM" uniphier-pcie to avoid randconfig errors

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-4.20-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy:
  phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845
  phy: qcom-qusb2: Use HSTX_TRIM fused value as is
  dt-bindings: phy-qcom-qmp: Fix several mistakes from prior commits
  phy: uniphier-pcie: Depend on HAS_IOMEM
parents 2e6e902d c88520db

Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

+23 −8
Original line number Diff line number Diff line
@@ -40,24 +40,36 @@ Required properties: 
		"ref" for 19.2 MHz ref clk,

		"com_aux" for phy common block aux clock,

		"ref_aux" for phy reference aux clock,



		For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.

		For "qcom,msm8996-qmp-pcie-phy" must contain:

			"aux", "cfg_ahb", "ref".

		For "qcom,msm8996-qmp-usb3-phy" must contain:

			"aux", "cfg_ahb", "ref".

		For "qcom,qmp-v3-usb3-phy" must contain:

		For "qcom,sdm845-qmp-usb3-phy" must contain:

			"aux", "cfg_ahb", "ref", "com_aux".

		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:

			"aux", "cfg_ahb", "ref", "com_aux".

		For "qcom,sdm845-qmp-ufs-phy" must contain:

			"ref", "ref_aux".



 - resets: a list of phandles and reset controller specifier pairs,

	   one for each entry in reset-names.

 - reset-names: "phy" for reset of phy block,

		"common" for phy common block reset,

		"cfg" for phy's ahb cfg block reset (Optional).

		"cfg" for phy's ahb cfg block reset.



		For "qcom,ipq8074-qmp-pcie-phy" must contain:

			"phy", "common".

		For "qcom,msm8996-qmp-pcie-phy" must contain:

			"phy", "common", "cfg".

		For "qcom,msm8996-qmp-usb3-phy" must contain

			"phy", "common".

		For "qcom,ipq8074-qmp-pcie-phy" must contain:

		For "qcom,sdm845-qmp-usb3-phy" must contain:

			"phy", "common".

		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:

			"phy", "common".

		For "qcom,sdm845-qmp-ufs-phy": no resets are listed.



 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.

 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -79,9 +91,10 @@ Required properties for child node: 


 - #phy-cells: must be 0



Required properties child node of pcie and usb3 qmp phys:

 - clocks: a list of phandles and clock-specifier pairs,

	   one for each entry in clock-names.

 - clock-names: Must contain following for pcie and usb qmp phys:

 - clock-names: Must contain following:

		 "pipe<lane-number>" for pipe clock specific to each lane.

 - clock-output-names: Name of the PHY clock that will be the parent for

		       the above pipe clock.
@@ -91,9 +104,11 @@ Required properties for child node: 
			(or)

		  "pcie20_phy1_pipe_clk"



Required properties for child node of PHYs with lane reset, AKA:

	"qcom,msm8996-qmp-pcie-phy"

 - resets: a list of phandles and reset controller specifier pairs,

	   one for each entry in reset-names.

 - reset-names: Must contain following for pcie qmp phys:

 - reset-names: Must contain following:

		 "lane<lane-number>" for reset specific to each lane.



Example:

drivers/phy/qualcomm/phy-qcom-qusb2.c

+11 −9
Original line number Diff line number Diff line
@@ -231,6 +231,7 @@ static const struct qusb2_phy_cfg sdm845_phy_cfg = { 
	.mask_core_ready = CORE_READY_STATUS,

	.has_pll_override = true,

	.autoresume_en	  = BIT(0),

	.update_tune1_with_efuse = true,

};



static const char * const qusb2_phy_vreg_names[] = {
@@ -402,10 +403,10 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 


	/*

	 * Read efuse register having TUNE2/1 parameter's high nibble.

	 * If efuse register shows value as 0x0, or if we fail to find

	 * a valid efuse register settings, then use default value

	 * as 0xB for high nibble that we have already set while

	 * configuring phy.

	 * If efuse register shows value as 0x0 (indicating value is not

	 * fused), or if we fail to find a valid efuse register setting,

	 * then use default value for high nibble that we have already

	 * set while configuring the phy.

	 */

	val = nvmem_cell_read(qphy->cell, NULL);

	if (IS_ERR(val) || !val[0]) {
@@ -415,12 +416,13 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 


	/* Fused TUNE1/2 value is the higher nibble only */

	if (cfg->update_tune1_with_efuse)

		qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],

			      val[0] << 0x4);

		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],

				 val[0] << HSTX_TRIM_SHIFT,

				 HSTX_TRIM_MASK);

	else

		qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],

			      val[0] << 0x4);



		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],

				 val[0] << HSTX_TRIM_SHIFT,

				 HSTX_TRIM_MASK);

}



static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)

drivers/phy/socionext/Kconfig

+2 −1
Original line number Diff line number Diff line
@@ -26,7 +26,8 @@ config PHY_UNIPHIER_USB3 


config PHY_UNIPHIER_PCIE

	tristate "Uniphier PHY driver for PCIe controller"

	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF

	depends on ARCH_UNIPHIER || COMPILE_TEST

	depends on OF && HAS_IOMEM

	default PCIE_UNIPHIER

	select GENERIC_PHY

	help

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