Commit 1db823ee authored by Lucas Stach's avatar Lucas Stach Committed by Bjorn Helgaas
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PCI: designware: Split Exynos and i.MX bindings 



The glue around the core designware IP is significantly different between
the Exynos and i.MX implementation, which is reflected in the DT bindings.

This changes the i.MX6 binding to reuse as much as possible from the common
designware binding and removes old cruft.

I removed the optional GPIOs with the following reasoning:
- disable-gpio: endpoint specific GPIO, not currently wired up in any code.
  Should be handled by the PCI device driver, not the host controller
  driver.
- wake-up-gpio: same as above.
- power-on-gpio: No user in any upstream DT.  This should be handled by a
  regulator which shouldn't be controlled by the host driver, but rather by
  the PCI device driver.

[bhelgaas: whitespace fixes]
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent d1dc9749

Documentation/devicetree/bindings/pci/designware-pcie.txt

+6 −68
Original line number Diff line number Diff line 
* Synopsys Designware PCIe interface



Required properties:

- compatible: should contain "snps,dw-pcie" to identify the

	core, plus an identifier for the specific instance, such

	as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".

- reg: base addresses and lengths of the pcie controller,

	the phy controller, additional register for the phy controller.

- interrupts: interrupt values for level interrupt,

	pulse interrupt, special interrupt.

- clocks: from common clock binding: handle to pci clock.

- clock-names: from common clock binding: should be "pcie" and "pcie_bus".

- compatible: should contain "snps,dw-pcie" to identify the core.

- #address-cells: set to <3>

- #size-cells: set to <2>

- device_type: set to "pci"
@@ -19,65 +11,11 @@ Required properties: 
	to define the mapping of the PCIe interface to interrupt

	numbers.

- num-lanes: number of lanes to use

- clocks: Must contain an entry for each entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

	- "pcie"

	- "pcie_bus"



Optional properties:

- reset-gpio: gpio pin number of power good signal
 


Optional properties for fsl,imx6q-pcie

- power-on-gpio: gpio pin number of power-enable signal

- wake-up-gpio: gpio pin number of incoming wakeup signal

- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal



Example:



SoC specific DT Entry:



	pcie@290000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000

			0x270000 0x1000

			0x271000 0x40>;

		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0x0 0 &gic 53>;

		num-lanes = <4>;

	};



	pcie@2a0000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x2a0000 0x1000

			0x272000 0x1000

			0x271040 0x40>;

		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;

		clocks = <&clock 29>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0x0 0 &gic 56>;

		num-lanes = <4>;

	};



Board specific DT Entry:



	pcie@290000 {

		reset-gpio = <&pin_ctrl 5 0>;

	};



	pcie@2a0000 {

		reset-gpio = <&pin_ctrl 22 0>;

	};

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

0 → 100644
+38 −0
Original line number Diff line number Diff line 
* Freescale i.MX6 PCIe interface



This PCIe host controller is based on the Synopsis Designware PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "fsl,imx6q-pcie"

- reg: base addresse and length of the pcie controller

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

	- "msi": The interrupt that is asserted when an MSI is received

- clock-names: Must include the following additional entries:

	- "pcie_phy"



Example:



	pcie@0x01000000 {

		compatible = "fsl,imx6q-pcie", "snps,dw-pcie";

		reg = <0x01ffc000 0x4000>;

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000

			  0x81000000 0 0          0x01f80000 0 0x00010000

			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;

		num-lanes = <1>;

		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clks 144>, <&clks 206>, <&clks 189>;

		clock-names = "pcie", "pcie_bus", "pcie_phy";

	};

Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt

0 → 100644
+65 −0
Original line number Diff line number Diff line 
* Samsung Exynos 5440 PCIe interface



This PCIe host controller is based on the Synopsis Designware PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "samsung,exynos5440-pcie"

- reg: base addresses and lengths of the pcie controller,

	the phy controller, additional register for the phy controller.

- interrupts: A list of interrupt outputs for level interrupt,

	pulse interrupt, special interrupt.



Example:



SoC specific DT Entry:



	pcie@290000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000

			0x270000 0x1000

			0x271000 0x40>;

		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



	pcie@2a0000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x2a0000 0x1000

			0x272000 0x1000

			0x271040 0x40>;

		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;

		clocks = <&clock 29>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



Board specific DT Entry:



	pcie@290000 {

		reset-gpio = <&pin_ctrl 5 0>;

	};



	pcie@2a0000 {

		reset-gpio = <&pin_ctrl 22 0>;

	};

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