Commit 1d5f497d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-3.19-dt' of... 

Merge tag 'tegra-for-3.19-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt2

Pull "ARM: tegra: Device tree changes for v3.19" from Thierry Reding:

The bulk of these changes add memory controller nodes for Tegra30,
Tegra114 and Tegra124. The memory controller implements an IOMMU that
the display controllers are attached to. This allows them to scan out
physically non-contiguous framebuffers and removes one of the primary
users of CMA.

The only other change adds a new MIPI pad control bank to the pin
controller on Tegra124. The corresponding driver patch for this went
into v3.18 as:

        3ccc11f6 pinctrl: tegra: Add MIPI pad control

* tag 'tegra-for-3.19-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  ARM: tegra: Enable IOMMU for display controllers on Tegra124
  ARM: tegra: Enable IOMMU for display controllers on Tegra114
  ARM: tegra: Enable IOMMU for display controllers on Tegra30
  ARM: tegra: Add memory controller support for Tegra124
  ARM: tegra: Add memory controller support for Tegra114
  ARM: tegra: Add memory controller support for Tegra30
  ARM: tegra: Add APB_MISC_GP as a MIPI pad control bank

These additional commits are merged as dependencies:

  memory: Add NVIDIA Tegra memory controller support
  of: Add NVIDIA Tegra memory controller binding
  ARM: tegra: Move AHB Kconfig to drivers/amba
  amba: Add Kconfig file
  clk: tegra: Implement memory-controller clock
  powerpc/iommu: Rename iommu_[un]map_sg functions
  iommu: Improve error handling when setting bus iommu
  iommu: Do more input validation in iommu_map_sg()
  iommu: Add iommu_map_sg() function

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 2f84411d 5b605d44

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt

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+36 −0
Original line number Diff line number Diff line 
NVIDIA Tegra Memory Controller device tree bindings

===================================================



Required properties:

- compatible: Should be "nvidia,tegra<chip>-mc"

- reg: Physical base address and length of the controller's registers.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts: The interrupt outputs from the controller.

- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines

  the SWGROUP of the master.



This device implements an IOMMU that complies with the generic IOMMU binding.

See ../iommu/iommu.txt for details.



Example:

--------



	mc: memory-controller@0,70019000 {

		compatible = "nvidia,tegra124-mc";

		reg = <0x0 0x70019000 0x0 0x1000>;

		clocks = <&tegra_car TEGRA124_CLK_MC>;

		clock-names = "mc";



		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;



		#iommu-cells = <1>;

	};



	sdhci@0,700b0000 {

		compatible = "nvidia,tegra124-sdhci";

		...

		iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;

	};

arch/arm/Kconfig

+0 −3
Original line number Diff line number Diff line
@@ -1259,9 +1259,6 @@ source "arch/arm/common/Kconfig" 


menu "Bus support"



config ARM_AMBA

	bool



config ISA

	bool

	help

arch/arm/boot/dts/tegra114.dtsi

+14 −9
Original line number Diff line number Diff line 
#include <dt-bindings/clock/tegra114-car.h>

#include <dt-bindings/gpio/tegra-gpio.h>

#include <dt-bindings/memory/tegra114-mc.h>

#include <dt-bindings/pinctrl/pinctrl-tegra.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -57,6 +58,8 @@ 
			resets = <&tegra_car 27>;

			reset-names = "dc";



			iommus = <&mc TEGRA_SWGROUP_DC>;



			nvidia,head = <0>;



			rgb {
@@ -74,6 +77,8 @@ 
			resets = <&tegra_car 26>;

			reset-names = "dc";



			iommus = <&mc TEGRA_SWGROUP_DCB>;



			nvidia,head = <1>;



			rgb {
@@ -505,15 +510,15 @@ 
		reset-names = "fuse";

	};



	iommu@70019010 {

		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";

		reg = <0x70019010 0x02c

		       0x700191f0 0x010

		       0x70019228 0x074>;

		nvidia,#asids = <4>;

		dma-window = <0 0x40000000>;

		nvidia,swgroups = <0x18659fe>;

		nvidia,ahb = <&ahb>;

	mc: memory-controller@70019000 {

		compatible = "nvidia,tegra114-mc";

		reg = <0x70019000 0x1000>;

		clocks = <&tegra_car TEGRA114_CLK_MC>;

		clock-names = "mc";



		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;



		#iommu-cells = <1>;

	};



	ahub@70080000 {

arch/arm/boot/dts/tegra124.dtsi

+18 −1
Original line number Diff line number Diff line 
#include <dt-bindings/clock/tegra124-car.h>

#include <dt-bindings/gpio/tegra-gpio.h>

#include <dt-bindings/memory/tegra124-mc.h>

#include <dt-bindings/pinctrl/pinctrl-tegra.h>

#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -102,6 +103,8 @@ 
			resets = <&tegra_car 27>;

			reset-names = "dc";



			iommus = <&mc TEGRA_SWGROUP_DC>;



			nvidia,head = <0>;

		};
@@ -115,6 +118,8 @@ 
			resets = <&tegra_car 26>;

			reset-names = "dc";



			iommus = <&mc TEGRA_SWGROUP_DCB>;



			nvidia,head = <1>;

		};
@@ -275,7 +280,8 @@ 
	pinmux: pinmux@0,70000868 {

		compatible = "nvidia,tegra124-pinmux";

		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */

		      <0x0 0x70003000 0x0 0x434>; /* Mux registers */

		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */

		      <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */

	};



	/*
@@ -551,6 +557,17 @@ 
		reset-names = "fuse";

	};



	mc: memory-controller@0,70019000 {

		compatible = "nvidia,tegra124-mc";

		reg = <0x0 0x70019000 0x0 0x1000>;

		clocks = <&tegra_car TEGRA124_CLK_MC>;

		clock-names = "mc";



		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;



		#iommu-cells = <1>;

	};



	sata@0,70020000 {

		compatible = "nvidia,tegra124-ahci";

arch/arm/boot/dts/tegra30.dtsi

+11 −14
Original line number Diff line number Diff line 
#include <dt-bindings/clock/tegra30-car.h>

#include <dt-bindings/gpio/tegra-gpio.h>

#include <dt-bindings/memory/tegra30-mc.h>

#include <dt-bindings/pinctrl/pinctrl-tegra.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -174,6 +175,8 @@ 
			resets = <&tegra_car 27>;

			reset-names = "dc";



			iommus = <&mc TEGRA_SWGROUP_DC>;



			nvidia,head = <0>;



			rgb {
@@ -191,6 +194,8 @@ 
			resets = <&tegra_car 26>;

			reset-names = "dc";



			iommus = <&mc TEGRA_SWGROUP_DCB>;



			nvidia,head = <1>;



			rgb {
@@ -623,23 +628,15 @@ 
		clock-names = "pclk", "clk32k_in";

	};



	memory-controller@7000f000 {

	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra30-mc";

		reg = <0x7000f000 0x010

		       0x7000f03c 0x1b4

		       0x7000f200 0x028

		       0x7000f284 0x17c>;

		reg = <0x7000f000 0x400>;

		clocks = <&tegra_car TEGRA30_CLK_MC>;

		clock-names = "mc";



		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

	};



	iommu@7000f010 {

		compatible = "nvidia,tegra30-smmu";

		reg = <0x7000f010 0x02c

		       0x7000f1f0 0x010

		       0x7000f228 0x05c>;

		nvidia,#asids = <4>;		/* # of ASIDs */

		dma-window = <0 0x40000000>;	/* IOVA start & length */

		nvidia,ahb = <&ahb>;

		#iommu-cells = <1>;

	};



	fuse@7000f800 {

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