Commit 1d5013f1 authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Sylwester Nawrocki
Browse files

clk: samsung: Add compile time PLL rate validators 



Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. To avoid possible mistakes we can use compile
time validation.
The patch introduces such validators and expands all initializers
with additional input frequency parameter, required to validate rates.
Since S3C24xx PLLs requires different validators two new macros have
been introduced to deal with it. Also, since PLLs 4502 and 4508 have
different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE.

As the patch adds only compile time validators it should not have impact
on compiled code.

Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: default avatarTomasz Figa <tomasz.figa@gmail.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 179db533

drivers/clk/samsung/clk-exynos3250.c

+57 −57
Original line number Diff line number Diff line
@@ -670,73 +670,73 @@ static const struct samsung_gate_clock gate_clks[] __initconst = { 


/* APLL & MPLL & BPLL & UPLL */

static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {

	PLL_35XX_RATE(1200000000, 400, 4, 1),

	PLL_35XX_RATE(1100000000, 275, 3, 1),

	PLL_35XX_RATE(1066000000, 533, 6, 1),

	PLL_35XX_RATE(1000000000, 250, 3, 1),

	PLL_35XX_RATE( 960000000, 320, 4, 1),

	PLL_35XX_RATE( 900000000, 300, 4, 1),

	PLL_35XX_RATE( 850000000, 425, 6, 1),

	PLL_35XX_RATE( 800000000, 200, 3, 1),

	PLL_35XX_RATE( 700000000, 175, 3, 1),

	PLL_35XX_RATE( 667000000, 667, 12, 1),

	PLL_35XX_RATE( 600000000, 400, 4, 2),

	PLL_35XX_RATE( 533000000, 533, 6, 2),

	PLL_35XX_RATE( 520000000, 260, 3, 2),

	PLL_35XX_RATE( 500000000, 250, 3, 2),

	PLL_35XX_RATE( 400000000, 200, 3, 2),

	PLL_35XX_RATE( 200000000, 200, 3, 3),

	PLL_35XX_RATE( 100000000, 200, 3, 4),

	PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),

	PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  960000000, 320, 4, 1),

	PLL_35XX_RATE(24 * MHZ,  900000000, 300, 4, 1),

	PLL_35XX_RATE(24 * MHZ,  850000000, 425, 6, 1),

	PLL_35XX_RATE(24 * MHZ,  800000000, 200, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  700000000, 175, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  667000000, 667, 12, 1),

	PLL_35XX_RATE(24 * MHZ,  600000000, 400, 4, 2),

	PLL_35XX_RATE(24 * MHZ,  533000000, 533, 6, 2),

	PLL_35XX_RATE(24 * MHZ,  520000000, 260, 3, 2),

	PLL_35XX_RATE(24 * MHZ,  500000000, 250, 3, 2),

	PLL_35XX_RATE(24 * MHZ,  400000000, 200, 3, 2),

	PLL_35XX_RATE(24 * MHZ,  200000000, 200, 3, 3),

	PLL_35XX_RATE(24 * MHZ,  100000000, 200, 3, 4),

	{ /* sentinel */ }

};



/* EPLL */

static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {

	PLL_36XX_RATE(800000000, 200, 3, 1,     0),

	PLL_36XX_RATE(288000000,  96, 2, 2,     0),

	PLL_36XX_RATE(192000000, 128, 2, 3,     0),

	PLL_36XX_RATE(144000000,  96, 2, 3,     0),

	PLL_36XX_RATE( 96000000, 128, 2, 4,     0),

	PLL_36XX_RATE( 84000000, 112, 2, 4,     0),

	PLL_36XX_RATE( 80000003, 106, 2, 4, 43691),

	PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),

	PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),

	PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),

	PLL_36XX_RATE( 50000000, 200, 3, 5,     0),

	PLL_36XX_RATE( 49152002, 131, 2, 5,  4719),

	PLL_36XX_RATE( 48000000, 128, 2, 5,     0),

	PLL_36XX_RATE( 45158401, 180, 3, 5, 41524),

	PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 288000000,  96, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 144000000,  96, 2, 3,     0),

	PLL_36XX_RATE(24 * MHZ,  96000000, 128, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  84000000, 112, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  80000003, 106, 2, 4, 43691),

	PLL_36XX_RATE(24 * MHZ,  73728000,  98, 2, 4, 19923),

	PLL_36XX_RATE(24 * MHZ,  67737598, 270, 3, 5, 62285),

	PLL_36XX_RATE(24 * MHZ,  65535999, 174, 2, 5, 49982),

	PLL_36XX_RATE(24 * MHZ,  50000000, 200, 3, 5,     0),

	PLL_36XX_RATE(24 * MHZ,  49152002, 131, 2, 5,  4719),

	PLL_36XX_RATE(24 * MHZ,  48000000, 128, 2, 5,     0),

	PLL_36XX_RATE(24 * MHZ,  45158401, 180, 3, 5, 41524),

	{ /* sentinel */ }

};



/* VPLL */

static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {

	PLL_36XX_RATE(600000000, 100, 2, 1,     0),

	PLL_36XX_RATE(533000000, 266, 3, 2, 32768),

	PLL_36XX_RATE(519230987, 173, 2, 2,  5046),

	PLL_36XX_RATE(500000000, 250, 3, 2,     0),

	PLL_36XX_RATE(445500000, 148, 2, 2, 32768),

	PLL_36XX_RATE(445055007, 148, 2, 2, 23047),

	PLL_36XX_RATE(400000000, 200, 3, 2,     0),

	PLL_36XX_RATE(371250000, 123, 2, 2, 49152),

	PLL_36XX_RATE(370878997, 185, 3, 2, 28803),

	PLL_36XX_RATE(340000000, 170, 3, 2,     0),

	PLL_36XX_RATE(335000015, 111, 2, 2, 43691),

	PLL_36XX_RATE(333000000, 111, 2, 2,     0),

	PLL_36XX_RATE(330000000, 110, 2, 2,     0),

	PLL_36XX_RATE(320000015, 106, 2, 2, 43691),

	PLL_36XX_RATE(300000000, 100, 2, 2,     0),

	PLL_36XX_RATE(275000000, 275, 3, 3,     0),

	PLL_36XX_RATE(222750000, 148, 2, 3, 32768),

	PLL_36XX_RATE(222528007, 148, 2, 3, 23069),

	PLL_36XX_RATE(160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(148500000,  99, 2, 3,     0),

	PLL_36XX_RATE(148352005,  98, 2, 3, 59070),

	PLL_36XX_RATE(108000000, 144, 2, 4,     0),

	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),

	PLL_36XX_RATE( 74176002,  98, 2, 4, 59070),

	PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),

	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),

	PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),

	PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2,  5046),

	PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),

	PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),

	PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),

	PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),

	PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),

	PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),

	PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),

	PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),

	PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 148500000,  99, 2, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 148352005,  98, 2, 3, 59070),

	PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  74250000,  99, 2, 4,     0),

	PLL_36XX_RATE(24 * MHZ,  74176002,  98, 2, 4, 59070),

	PLL_36XX_RATE(24 * MHZ,  54054000, 216, 3, 5, 14156),

	PLL_36XX_RATE(24 * MHZ,  54000000, 144, 2, 5,     0),

	{ /* sentinel */ }

};

drivers/clk/samsung/clk-exynos4.c

+51 −51
Original line number Diff line number Diff line
@@ -1266,77 +1266,77 @@ static const struct of_device_id ext_clk_match[] __initconst = { 


/* PLLs PMS values */

static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {

	PLL_45XX_RATE(1200000000, 150,  3, 1, 28),

	PLL_45XX_RATE(1000000000, 250,  6, 1, 28),

	PLL_45XX_RATE( 800000000, 200,  6, 1, 28),

	PLL_45XX_RATE( 666857142, 389, 14, 1, 13),

	PLL_45XX_RATE( 600000000, 100,  4, 1, 13),

	PLL_45XX_RATE( 533000000, 533, 24, 1,  5),

	PLL_45XX_RATE( 500000000, 250,  6, 2, 28),

	PLL_45XX_RATE( 400000000, 200,  6, 2, 28),

	PLL_45XX_RATE( 200000000, 200,  6, 3, 28),

	PLL_4508_RATE(24 * MHZ, 1200000000, 150,  3, 1, 28),

	PLL_4508_RATE(24 * MHZ, 1000000000, 250,  6, 1, 28),

	PLL_4508_RATE(24 * MHZ,  800000000, 200,  6, 1, 28),

	PLL_4508_RATE(24 * MHZ,  666857142, 389, 14, 1, 13),

	PLL_4508_RATE(24 * MHZ,  600000000, 100,  4, 1, 13),

	PLL_4508_RATE(24 * MHZ,  533000000, 533, 24, 1,  5),

	PLL_4508_RATE(24 * MHZ,  500000000, 250,  6, 2, 28),

	PLL_4508_RATE(24 * MHZ,  400000000, 200,  6, 2, 28),

	PLL_4508_RATE(24 * MHZ,  200000000, 200,  6, 3, 28),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {

	PLL_4600_RATE(192000000, 48, 3, 1,     0, 0),

	PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),

	PLL_4600_RATE(180000000, 45, 3, 1,     0, 0),

	PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),

	PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),

	PLL_4600_RATE( 49151992, 49, 3, 3,  9961, 0),

	PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),

	PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1,     0, 0),

	PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),

	PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1,     0, 0),

	PLL_4600_RATE(24 * MHZ,  73727996, 73, 3, 3, 47710, 1),

	PLL_4600_RATE(24 * MHZ,  67737602, 90, 4, 3, 20762, 1),

	PLL_4600_RATE(24 * MHZ,  49151992, 49, 3, 3,  9961, 0),

	PLL_4600_RATE(24 * MHZ,  45158401, 45, 3, 3, 10381, 0),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {

	PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),

	PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1,  1, 1),

	PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),

	PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0),

	PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),

	PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),

	PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1,  1, 1),

	PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),

	PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),

	PLL_4650_RATE(24 * MHZ,  55360351, 53, 3, 3, 2417, 0, 17, 0),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {

	PLL_35XX_RATE(1704000000, 213, 3, 0),

	PLL_35XX_RATE(1600000000, 200, 3, 0),

	PLL_35XX_RATE(1500000000, 250, 4, 0),

	PLL_35XX_RATE(1400000000, 175, 3, 0),

	PLL_35XX_RATE(1300000000, 325, 6, 0),

	PLL_35XX_RATE(1200000000, 200, 4, 0),

	PLL_35XX_RATE(1100000000, 275, 6, 0),

	PLL_35XX_RATE(1000000000, 125, 3, 0),

	PLL_35XX_RATE( 900000000, 150, 4, 0),

	PLL_35XX_RATE( 800000000, 100, 3, 0),

	PLL_35XX_RATE( 700000000, 175, 3, 1),

	PLL_35XX_RATE( 600000000, 200, 4, 1),

	PLL_35XX_RATE( 500000000, 125, 3, 1),

	PLL_35XX_RATE( 400000000, 100, 3, 1),

	PLL_35XX_RATE( 300000000, 200, 4, 2),

	PLL_35XX_RATE( 200000000, 100, 3, 2),

	PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),

	PLL_35XX_RATE(24 * MHZ,  900000000, 150, 4, 0),

	PLL_35XX_RATE(24 * MHZ,  800000000, 100, 3, 0),

	PLL_35XX_RATE(24 * MHZ,  700000000, 175, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  600000000, 200, 4, 1),

	PLL_35XX_RATE(24 * MHZ,  500000000, 125, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  400000000, 100, 3, 1),

	PLL_35XX_RATE(24 * MHZ,  300000000, 200, 4, 2),

	PLL_35XX_RATE(24 * MHZ,  200000000, 100, 3, 2),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {

	PLL_36XX_RATE(192000000, 48, 3, 1,     0),

	PLL_36XX_RATE(180633605, 45, 3, 1, 10381),

	PLL_36XX_RATE(180000000, 45, 3, 1,     0),

	PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),

	PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),

	PLL_36XX_RATE( 49151992, 49, 3, 3,  9961),

	PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),

	PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),

	PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ,  73727996, 73, 3, 3, 47710),

	PLL_36XX_RATE(24 * MHZ,  67737602, 90, 4, 3, 20762),

	PLL_36XX_RATE(24 * MHZ,  49151992, 49, 3, 3,  9961),

	PLL_36XX_RATE(24 * MHZ,  45158401, 45, 3, 3, 10381),

	{ /* sentinel */ }

};



static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {

	PLL_36XX_RATE(533000000, 133, 3, 1, 16384),

	PLL_36XX_RATE(440000000, 110, 3, 1,     0),

	PLL_36XX_RATE(350000000, 175, 3, 2,     0),

	PLL_36XX_RATE(266000000, 133, 3, 2,     0),

	PLL_36XX_RATE(160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(106031250,  53, 3, 2,  1024),

	PLL_36XX_RATE( 53015625,  53, 3, 3,  1024),

	PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),

	PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1,     0),

	PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2,     0),

	PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3,     0),

	PLL_36XX_RATE(24 * MHZ, 106031250,  53, 3, 2,  1024),

	PLL_36XX_RATE(24 * MHZ,  53015625,  53, 3, 3,  1024),

	{ /* sentinel */ }

};

drivers/clk/samsung/clk-exynos5250.c

+27 −27
Original line number Diff line number Diff line
@@ -701,45 +701,45 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { 
static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {

	/* sorted in descending order */

	/* PLL_36XX_RATE(rate, m, p, s, k) */

	PLL_36XX_RATE(266000000, 266, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),

	/* Not in UM, but need for eDP on snow */

	PLL_36XX_RATE(70500000, 94, 2, 4, 0),

	PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),

	{ },

};



static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {

	/* sorted in descending order */

	/* PLL_36XX_RATE(rate, m, p, s, k) */

	PLL_36XX_RATE(192000000, 64, 2, 2, 0),

	PLL_36XX_RATE(180633605, 90, 3, 2, 20762),

	PLL_36XX_RATE(180000000, 90, 3, 2, 0),

	PLL_36XX_RATE(73728000, 98, 2, 4, 19923),

	PLL_36XX_RATE(67737602, 90, 2, 4, 20762),

	PLL_36XX_RATE(49152000, 98, 3, 4, 19923),

	PLL_36XX_RATE(45158401, 90, 3, 4, 20762),

	PLL_36XX_RATE(32768001, 131, 3, 5, 4719),

	PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),

	PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),

	PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),

	PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),

	PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),

	PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),

	{ },

};



static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {

	/* sorted in descending order */

	/* PLL_35XX_RATE(rate, m, p, s) */

	PLL_35XX_RATE(1700000000, 425, 6, 0),

	PLL_35XX_RATE(1600000000, 200, 3, 0),

	PLL_35XX_RATE(1500000000, 250, 4, 0),

	PLL_35XX_RATE(1400000000, 175, 3, 0),

	PLL_35XX_RATE(1300000000, 325, 6, 0),

	PLL_35XX_RATE(1200000000, 200, 4, 0),

	PLL_35XX_RATE(1100000000, 275, 6, 0),

	PLL_35XX_RATE(1000000000, 125, 3, 0),

	PLL_35XX_RATE(900000000, 150, 4, 0),

	PLL_35XX_RATE(800000000, 100, 3, 0),

	PLL_35XX_RATE(700000000, 175, 3, 1),

	PLL_35XX_RATE(600000000, 200, 4, 1),

	PLL_35XX_RATE(500000000, 125, 3, 1),

	PLL_35XX_RATE(400000000, 100, 3, 1),

	PLL_35XX_RATE(300000000, 200, 4, 2),

	PLL_35XX_RATE(200000000, 100, 3, 2),

	/* PLL_35XX_RATE(fin, rate, m, p, s) */

	PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),

	PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),

};



static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {

drivers/clk/samsung/clk-exynos5260.c

+45 −45
Original line number Diff line number Diff line
@@ -23,57 +23,57 @@ 
 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.

 */

static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {

	PLL_35XX_RATE(1700000000, 425, 6, 0),

	PLL_35XX_RATE(1600000000, 200, 3, 0),

	PLL_35XX_RATE(1500000000, 250, 4, 0),

	PLL_35XX_RATE(1400000000, 175, 3, 0),

	PLL_35XX_RATE(1300000000, 325, 6, 0),

	PLL_35XX_RATE(1200000000, 400, 4, 1),

	PLL_35XX_RATE(1100000000, 275, 3, 1),

	PLL_35XX_RATE(1000000000, 250, 3, 1),

	PLL_35XX_RATE(933000000, 311, 4, 1),

	PLL_35XX_RATE(900000000, 300, 4, 1),

	PLL_35XX_RATE(800000000, 200, 3, 1),

	PLL_35XX_RATE(733000000, 733, 12, 1),

	PLL_35XX_RATE(700000000, 175, 3, 1),

	PLL_35XX_RATE(667000000, 667, 12, 1),

	PLL_35XX_RATE(633000000, 211, 4, 1),

	PLL_35XX_RATE(620000000, 310, 3, 2),

	PLL_35XX_RATE(600000000, 400, 4, 2),

	PLL_35XX_RATE(543000000, 362, 4, 2),

	PLL_35XX_RATE(533000000, 533, 6, 2),

	PLL_35XX_RATE(500000000, 250, 3, 2),

	PLL_35XX_RATE(450000000, 300, 4, 2),

	PLL_35XX_RATE(400000000, 200, 3, 2),

	PLL_35XX_RATE(350000000, 175, 3, 2),

	PLL_35XX_RATE(300000000, 400, 4, 3),

	PLL_35XX_RATE(266000000, 266, 3, 3),

	PLL_35XX_RATE(200000000, 200, 3, 3),

	PLL_35XX_RATE(160000000, 160, 3, 3),

	PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),

	PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),

	PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),

	PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),

	PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),

	PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),

	PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),

	PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),

	PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),

	PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),

	PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),

	PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),

	PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),

	PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),

	PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),

	PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),

	PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),

};



/*

 * Applicable for 2650 Type PLL for AUD_PLL.

 */

static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {

	PLL_36XX_RATE(1600000000, 200, 3, 0, 0),

	PLL_36XX_RATE(1200000000, 100, 2, 0, 0),

	PLL_36XX_RATE(1000000000, 250, 3, 1, 0),

	PLL_36XX_RATE(800000000, 200, 3, 1, 0),

	PLL_36XX_RATE(600000000, 100, 2, 1, 0),

	PLL_36XX_RATE(532000000, 266, 3, 2, 0),

	PLL_36XX_RATE(480000000, 160, 2, 2, 0),

	PLL_36XX_RATE(432000000, 144, 2, 2, 0),

	PLL_36XX_RATE(400000000, 200, 3, 2, 0),

	PLL_36XX_RATE(394073128, 459, 7, 2, 49282),

	PLL_36XX_RATE(333000000, 111, 2, 2, 0),

	PLL_36XX_RATE(300000000, 100, 2, 2, 0),

	PLL_36XX_RATE(266000000, 266, 3, 3, 0),

	PLL_36XX_RATE(200000000, 200, 3, 3, 0),

	PLL_36XX_RATE(166000000, 166, 3, 3, 0),

	PLL_36XX_RATE(133000000, 266, 3, 4, 0),

	PLL_36XX_RATE(100000000, 200, 3, 4, 0),

	PLL_36XX_RATE(66000000, 176, 2, 5, 0),

	PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),

	PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),

	PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),

	PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),

	PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),

	PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),

	PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),

	PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),

	PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),

};



/* CMU_AUD */

drivers/clk/samsung/clk-exynos5410.c

+10 −10
Original line number Diff line number Diff line
@@ -226,16 +226,16 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { 
};



static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = {

	PLL_36XX_RATE(400000000U, 200, 3, 2, 0),

	PLL_36XX_RATE(333000000U, 111, 2, 2, 0),

	PLL_36XX_RATE(300000000U, 100, 2, 2, 0),

	PLL_36XX_RATE(266000000U, 266, 3, 3, 0),

	PLL_36XX_RATE(200000000U, 200, 3, 3, 0),

	PLL_36XX_RATE(192000000U, 192, 3, 3, 0),

	PLL_36XX_RATE(166000000U, 166, 3, 3, 0),

	PLL_36XX_RATE(133000000U, 266, 3, 4, 0),

	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),

	PLL_36XX_RATE(66000000U,  176, 2, 5, 0),

	PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),

	PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),

	PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),

	PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),

	PLL_36XX_RATE(24 * MHZ, 66000000U,  176, 2, 5, 0),

};



static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {

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