Commit 1d23b65d authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
Browse files

[ARM] 3126/1: BAST: fix map_desc initialisation 



Patch from Ben Dooks

Fix the map_desc entries to use the new .pfn
initialiser for the Simtec BAST machine support.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent df1ec6de

arch/arm/mach-s3c2410/mach-bast.c

+52 −21
Original line number Diff line number Diff line
@@ -89,32 +89,63 @@ 


/* macros to modify the physical addresses for io space */



#define PA_CS2(item) ((item) + S3C2410_CS2)

#define PA_CS3(item) ((item) + S3C2410_CS3)

#define PA_CS4(item) ((item) + S3C2410_CS4)

#define PA_CS5(item) ((item) + S3C2410_CS5)

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))

#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))

#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))

#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))



static struct map_desc bast_iodesc[] __initdata = {

  /* ISA IO areas */



  { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO),   SZ_16M, MT_DEVICE },

  { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO),   SZ_16M, MT_DEVICE },



  /* we could possibly compress the next set down into a set of smaller tables

   * pagetables, but that would mean using an L2 section, and it still means

   * we cannot actually feed the same register to an LDR due to 16K spacing

   */



  {

	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,

	  .pfn		= PA_CS2(BAST_PA_ISAIO),

	  .length	= SZ_16M,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,

	  .pfn		= PA_CS3(BAST_PA_ISAIO),

	  .length	= SZ_16M,

	  .type		= MT_DEVICE,

  },

  /* bast CPLD control registers, and external interrupt controls */

  { (u32)BAST_VA_CTRL1, BAST_PA_CTRL1,		   SZ_1M, MT_DEVICE },

  { (u32)BAST_VA_CTRL2, BAST_PA_CTRL2,		   SZ_1M, MT_DEVICE },

  { (u32)BAST_VA_CTRL3, BAST_PA_CTRL3,		   SZ_1M, MT_DEVICE },

  { (u32)BAST_VA_CTRL4, BAST_PA_CTRL4,		   SZ_1M, MT_DEVICE },



  {

	  .virtual	= (u32)BAST_VA_CTRL1,

	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),

	  .length	= SZ_1M,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)BAST_VA_CTRL2,

	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),

	  .length	= SZ_1M,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)BAST_VA_CTRL3,

	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),

	  .length	= SZ_1M,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)BAST_VA_CTRL4,

	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),

	  .length	= SZ_1M,

	  .type		= MT_DEVICE,

  },

  /* PC104 IRQ mux */

  { (u32)BAST_VA_PC104_IRQREQ,  BAST_PA_PC104_IRQREQ,   SZ_1M, MT_DEVICE },

  { (u32)BAST_VA_PC104_IRQRAW,  BAST_PA_PC104_IRQRAW,   SZ_1M, MT_DEVICE },

  { (u32)BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK,  SZ_1M, MT_DEVICE },

  {

	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,

	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),

	  .length	= SZ_1M,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,

	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),

	  .length	= SZ_1M,

	  .type		= MT_DEVICE,

  }, {

	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,

	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),

	  .length	= SZ_1M,

	  .type		= MT_DEVICE,

  },



  /* peripheral space... one for each of fast/slow/byte/16bit */

  /* note, ide is only decoded in word space, even though some registers

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