coresight: dts: binding: Update coresight binding examples (1cf11385) · Commits · 戴 / test

While we updated the coresight DT bindings, some of the new examples were not updated due to the order in which they were merged. Let us update all the missed out ones to the new bindings to avoid confusion. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: Frank Rowand <frowand.list@gmail.com> Signed-off-by:

Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by:

Rob Herring <robh@kernel.org> Signed-off-by:

Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:

Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Documentation/devicetree/bindings/arm/coresight.txt

+10 −15

Original line number	Diff line number	Diff line
		@@ -147,22 +147,16 @@ Example:

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		/* input port */
		port@0 {
		reg = <0>;
		in-ports {
		port {
		etr_in_port: endpoint {
		slave-mode;
		remote-endpoint = <&replicator2_out_port0>;
		};
		};
		};

		/* CATU link represented by output port */
		port@1 {
		reg = <1>;
		out-ports {
		port {
		etr_out_port: endpoint {
		remote-endpoint = <&catu_in_port>;
		};
		@@ -310,13 +304,14 @@ Example:
		clock-names = "apb_pclk";

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		in-ports {
		port {
		catu_in_port: endpoint {
		slave-mode;
		remote-endpoint = <&etr_out_port>;
		};
		};
		};
		};

		[1]. There is currently two version of STM: STM32 and STM500. Both
		have the same HW interface and as such don't need an explicit binding name.

Admin message