Commit 1cc6ed90 authored by Mark Rutland's avatar Mark Rutland Committed by Catalin Marinas
Browse files

arm64: make mrs_s prefixing implicit in read_cpuid 



Commit 0f54b14e ("arm64: cpufeature: Change read_cpuid() to use
sysreg's mrs_s macro") changed read_cpuid to require a SYS_ prefix on
register names, to allow manual assembly of registers unknown by the
toolchain, using tables in sysreg.h.

This interacts poorly with commit 42b55734 ("efi/arm64: Check
for h/w support before booting a >4 KB granular kernel"), which is
curretly queued via the tip tree, and uses read_cpuid without a SYS_
prefix. Due to this, a build of next-20160304 fails if EFI and 64K pages
are selected.

To avoid this issue when trees are merged, move the required SYS_
prefixing into read_cpuid, and revert all of the updated callsites to
pass plain register names. This effectively reverts the bulk of commit
0f54b14e.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 57efac2f

arch/arm64/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ u64 read_system_reg(u32 id); 


static inline bool cpu_supports_mixed_endian_el0(void)

{

	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1));

	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));

}



static inline bool system_supports_mixed_endian_el0(void)

arch/arm64/include/asm/cputype.h

+4 −4
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ 


#define read_cpuid(reg) ({						\

	u64 __val;							\

	asm("mrs_s	%0, " __stringify(reg) : "=r" (__val));		\

	asm("mrs_s	%0, " __stringify(SYS_ ## reg) : "=r" (__val));	\

	__val;								\

})
@@ -101,12 +101,12 @@ 
 */

static inline u32 __attribute_const__ read_cpuid_id(void)

{

	return read_cpuid(SYS_MIDR_EL1);

	return read_cpuid(MIDR_EL1);

}



static inline u64 __attribute_const__ read_cpuid_mpidr(void)

{

	return read_cpuid(SYS_MPIDR_EL1);

	return read_cpuid(MPIDR_EL1);

}



static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
@@ -121,7 +121,7 @@ static inline unsigned int __attribute_const__ read_cpuid_part_number(void) 


static inline u32 __attribute_const__ read_cpuid_cachetype(void)

{

	return read_cpuid(SYS_CTR_EL0);

	return read_cpuid(CTR_EL0);

}

#endif /* __ASSEMBLY__ */

arch/arm64/kernel/cpufeature.c

+30 −30
Original line number Diff line number Diff line
@@ -855,36 +855,36 @@ static inline void set_sys_caps_initialised(void) 
static u64 __raw_read_system_reg(u32 sys_id)

{

	switch (sys_id) {

	case SYS_ID_PFR0_EL1:		return read_cpuid(SYS_ID_PFR0_EL1);

	case SYS_ID_PFR1_EL1:		return read_cpuid(SYS_ID_PFR1_EL1);

	case SYS_ID_DFR0_EL1:		return read_cpuid(SYS_ID_DFR0_EL1);

	case SYS_ID_MMFR0_EL1:		return read_cpuid(SYS_ID_MMFR0_EL1);

	case SYS_ID_MMFR1_EL1:		return read_cpuid(SYS_ID_MMFR1_EL1);

	case SYS_ID_MMFR2_EL1:		return read_cpuid(SYS_ID_MMFR2_EL1);

	case SYS_ID_MMFR3_EL1:		return read_cpuid(SYS_ID_MMFR3_EL1);

	case SYS_ID_ISAR0_EL1:		return read_cpuid(SYS_ID_ISAR0_EL1);

	case SYS_ID_ISAR1_EL1:		return read_cpuid(SYS_ID_ISAR1_EL1);

	case SYS_ID_ISAR2_EL1:		return read_cpuid(SYS_ID_ISAR2_EL1);

	case SYS_ID_ISAR3_EL1:		return read_cpuid(SYS_ID_ISAR3_EL1);

	case SYS_ID_ISAR4_EL1:		return read_cpuid(SYS_ID_ISAR4_EL1);

	case SYS_ID_ISAR5_EL1:		return read_cpuid(SYS_ID_ISAR4_EL1);

	case SYS_MVFR0_EL1:		return read_cpuid(SYS_MVFR0_EL1);

	case SYS_MVFR1_EL1:		return read_cpuid(SYS_MVFR1_EL1);

	case SYS_MVFR2_EL1:		return read_cpuid(SYS_MVFR2_EL1);



	case SYS_ID_AA64PFR0_EL1:	return read_cpuid(SYS_ID_AA64PFR0_EL1);

	case SYS_ID_AA64PFR1_EL1:	return read_cpuid(SYS_ID_AA64PFR0_EL1);

	case SYS_ID_AA64DFR0_EL1:	return read_cpuid(SYS_ID_AA64DFR0_EL1);

	case SYS_ID_AA64DFR1_EL1:	return read_cpuid(SYS_ID_AA64DFR0_EL1);

	case SYS_ID_AA64MMFR0_EL1:	return read_cpuid(SYS_ID_AA64MMFR0_EL1);

	case SYS_ID_AA64MMFR1_EL1:	return read_cpuid(SYS_ID_AA64MMFR1_EL1);

	case SYS_ID_AA64MMFR2_EL1:	return read_cpuid(SYS_ID_AA64MMFR2_EL1);

	case SYS_ID_AA64ISAR0_EL1:	return read_cpuid(SYS_ID_AA64ISAR0_EL1);

	case SYS_ID_AA64ISAR1_EL1:	return read_cpuid(SYS_ID_AA64ISAR1_EL1);



	case SYS_CNTFRQ_EL0:		return read_cpuid(SYS_CNTFRQ_EL0);

	case SYS_CTR_EL0:		return read_cpuid(SYS_CTR_EL0);

	case SYS_DCZID_EL0:		return read_cpuid(SYS_DCZID_EL0);

	case SYS_ID_PFR0_EL1:		return read_cpuid(ID_PFR0_EL1);

	case SYS_ID_PFR1_EL1:		return read_cpuid(ID_PFR1_EL1);

	case SYS_ID_DFR0_EL1:		return read_cpuid(ID_DFR0_EL1);

	case SYS_ID_MMFR0_EL1:		return read_cpuid(ID_MMFR0_EL1);

	case SYS_ID_MMFR1_EL1:		return read_cpuid(ID_MMFR1_EL1);

	case SYS_ID_MMFR2_EL1:		return read_cpuid(ID_MMFR2_EL1);

	case SYS_ID_MMFR3_EL1:		return read_cpuid(ID_MMFR3_EL1);

	case SYS_ID_ISAR0_EL1:		return read_cpuid(ID_ISAR0_EL1);

	case SYS_ID_ISAR1_EL1:		return read_cpuid(ID_ISAR1_EL1);

	case SYS_ID_ISAR2_EL1:		return read_cpuid(ID_ISAR2_EL1);

	case SYS_ID_ISAR3_EL1:		return read_cpuid(ID_ISAR3_EL1);

	case SYS_ID_ISAR4_EL1:		return read_cpuid(ID_ISAR4_EL1);

	case SYS_ID_ISAR5_EL1:		return read_cpuid(ID_ISAR4_EL1);

	case SYS_MVFR0_EL1:		return read_cpuid(MVFR0_EL1);

	case SYS_MVFR1_EL1:		return read_cpuid(MVFR1_EL1);

	case SYS_MVFR2_EL1:		return read_cpuid(MVFR2_EL1);



	case SYS_ID_AA64PFR0_EL1:	return read_cpuid(ID_AA64PFR0_EL1);

	case SYS_ID_AA64PFR1_EL1:	return read_cpuid(ID_AA64PFR0_EL1);

	case SYS_ID_AA64DFR0_EL1:	return read_cpuid(ID_AA64DFR0_EL1);

	case SYS_ID_AA64DFR1_EL1:	return read_cpuid(ID_AA64DFR0_EL1);

	case SYS_ID_AA64MMFR0_EL1:	return read_cpuid(ID_AA64MMFR0_EL1);

	case SYS_ID_AA64MMFR1_EL1:	return read_cpuid(ID_AA64MMFR1_EL1);

	case SYS_ID_AA64MMFR2_EL1:	return read_cpuid(ID_AA64MMFR2_EL1);

	case SYS_ID_AA64ISAR0_EL1:	return read_cpuid(ID_AA64ISAR0_EL1);

	case SYS_ID_AA64ISAR1_EL1:	return read_cpuid(ID_AA64ISAR1_EL1);



	case SYS_CNTFRQ_EL0:		return read_cpuid(CNTFRQ_EL0);

	case SYS_CTR_EL0:		return read_cpuid(CTR_EL0);

	case SYS_DCZID_EL0:		return read_cpuid(DCZID_EL0);

	default:

		BUG();

		return 0;

arch/arm64/kernel/cpuinfo.c

+28 −28
Original line number Diff line number Diff line
@@ -203,36 +203,36 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
{

	info->reg_cntfrq = arch_timer_get_cntfrq();

	info->reg_ctr = read_cpuid_cachetype();

	info->reg_dczid = read_cpuid(SYS_DCZID_EL0);

	info->reg_dczid = read_cpuid(DCZID_EL0);

	info->reg_midr = read_cpuid_id();



	info->reg_id_aa64dfr0 = read_cpuid(SYS_ID_AA64DFR0_EL1);

	info->reg_id_aa64dfr1 = read_cpuid(SYS_ID_AA64DFR1_EL1);

	info->reg_id_aa64isar0 = read_cpuid(SYS_ID_AA64ISAR0_EL1);

	info->reg_id_aa64isar1 = read_cpuid(SYS_ID_AA64ISAR1_EL1);

	info->reg_id_aa64mmfr0 = read_cpuid(SYS_ID_AA64MMFR0_EL1);

	info->reg_id_aa64mmfr1 = read_cpuid(SYS_ID_AA64MMFR1_EL1);

	info->reg_id_aa64mmfr2 = read_cpuid(SYS_ID_AA64MMFR2_EL1);

	info->reg_id_aa64pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1);

	info->reg_id_aa64pfr1 = read_cpuid(SYS_ID_AA64PFR1_EL1);



	info->reg_id_dfr0 = read_cpuid(SYS_ID_DFR0_EL1);

	info->reg_id_isar0 = read_cpuid(SYS_ID_ISAR0_EL1);

	info->reg_id_isar1 = read_cpuid(SYS_ID_ISAR1_EL1);

	info->reg_id_isar2 = read_cpuid(SYS_ID_ISAR2_EL1);

	info->reg_id_isar3 = read_cpuid(SYS_ID_ISAR3_EL1);

	info->reg_id_isar4 = read_cpuid(SYS_ID_ISAR4_EL1);

	info->reg_id_isar5 = read_cpuid(SYS_ID_ISAR5_EL1);

	info->reg_id_mmfr0 = read_cpuid(SYS_ID_MMFR0_EL1);

	info->reg_id_mmfr1 = read_cpuid(SYS_ID_MMFR1_EL1);

	info->reg_id_mmfr2 = read_cpuid(SYS_ID_MMFR2_EL1);

	info->reg_id_mmfr3 = read_cpuid(SYS_ID_MMFR3_EL1);

	info->reg_id_pfr0 = read_cpuid(SYS_ID_PFR0_EL1);

	info->reg_id_pfr1 = read_cpuid(SYS_ID_PFR1_EL1);



	info->reg_mvfr0 = read_cpuid(SYS_MVFR0_EL1);

	info->reg_mvfr1 = read_cpuid(SYS_MVFR1_EL1);

	info->reg_mvfr2 = read_cpuid(SYS_MVFR2_EL1);

	info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);

	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);

	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);

	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);

	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);

	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);

	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);

	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);

	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);



	info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);

	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);

	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);

	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);

	info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);

	info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);

	info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);

	info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);

	info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);

	info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);

	info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);

	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);

	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);



	info->reg_mvfr0 = read_cpuid(MVFR0_EL1);

	info->reg_mvfr1 = read_cpuid(MVFR1_EL1);

	info->reg_mvfr2 = read_cpuid(MVFR2_EL1);



	cpuinfo_detect_icache_policy(info);

arch/arm64/mm/context.c

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ static cpumask_t tlb_flush_pending; 
static u32 get_cpu_asid_bits(void)

{

	u32 asid;

	int fld = cpuid_feature_extract_unsigned_field(read_cpuid(SYS_ID_AA64MMFR0_EL1),

	int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1),

						ID_AA64MMFR0_ASID_SHIFT);



	switch (fld) {

CRA Git | Maintained and supported by SUSTech CRA and CCSE