Commit 1caba4e8 authored by Aric Cyr's avatar Aric Cyr Committed by Alex Deucher
Browse files

drm/amd/display: Update V_UPDATE whenever VSTARTUP changes



[Why]
If VSTARTUP changes due to bandwidth requirements, we must
recalculate and update VLINE2 as well for proper flip reporting.

[How]
After all calls to program_global_sync which reconfigures
VSTARTUP, also make sure to update V_UPDATE (i.e. VLINE2 on DCNx).

Signed-off-by: default avatarAric Cyr <aric.cyr@amd.com>
Reviewed-by: default avatarSivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cbc697b2
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+3 −1
Original line number Diff line number Diff line
@@ -2511,8 +2511,10 @@ static void program_all_pipe_in_tree(
		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
		if (dc->hwss.setup_vupdate_interrupt)
			dc->hwss.setup_vupdate_interrupt(pipe_ctx);

		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
	}

	if (pipe_ctx->plane_state != NULL)
+7 −0
Original line number Diff line number Diff line
@@ -1370,6 +1370,9 @@ static void dcn20_program_pipe(

		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

		if (dc->hwss.setup_vupdate_interrupt)
			dc->hwss.setup_vupdate_interrupt(pipe_ctx);
	}

	if (pipe_ctx->update_flags.bits.odm)
@@ -1581,8 +1584,12 @@ bool dcn20_update_bandwidth(

			pipe_ctx->stream_res.tg->funcs->set_vtg_params(
					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

			if (pipe_ctx->prev_odm_pipe == NULL)
				dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);

			if (dc->hwss.setup_vupdate_interrupt)
				dc->hwss.setup_vupdate_interrupt(pipe_ctx);
		}

		pipe_ctx->plane_res.hubp->funcs->hubp_setup(