Commit 1ca9db5b authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/32: save DEAR/DAR before calling handle_page_fault 



handle_page_fault() is the only function that save DAR/DEAR itself.

Save DAR/DEAR before calling handle_page_fault() to prepare for
VMAP stack which will require to save even before.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/3a4d58d378091086f00fde42b59610c80289e120.1576916812.git.christophe.leroy@c-s.fr
parent 1f1c4d01

arch/powerpc/kernel/entry_32.S

+0 −1
Original line number Diff line number Diff line
@@ -621,7 +621,6 @@ ppc_swapcontext: 
 */

	.globl	handle_page_fault

handle_page_fault:

	stw	r4,_DAR(r1)

	addi	r3,r1,STACK_FRAME_OVERHEAD

#ifdef CONFIG_PPC_BOOK3S_32

	andis.  r0,r5,DSISR_DABRMATCH@h

arch/powerpc/kernel/head_32.S

+2 −0
Original line number Diff line number Diff line
@@ -310,6 +310,7 @@ BEGIN_MMU_FTR_SECTION 
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)

1:	lwz	r5,_DSISR(r11)		/* get DSISR value */

	mfspr	r4,SPRN_DAR

	stw	r4, _DAR(r11)

	EXC_XFER_LITE(0x300, handle_page_fault)
@@ -327,6 +328,7 @@ BEGIN_MMU_FTR_SECTION 
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)

1:	mr	r4,r12

	andis.	r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */

	stw	r4, _DAR(r11)

	EXC_XFER_LITE(0x400, handle_page_fault)



/* External interrupt */

arch/powerpc/kernel/head_40x.S

+2 −0
Original line number Diff line number Diff line
@@ -313,6 +313,7 @@ _ENTRY(saved_ksp_limit) 
	START_EXCEPTION(0x0400, InstructionAccess)

	EXCEPTION_PROLOG

	mr	r4,r12			/* Pass SRR0 as arg2 */

	stw	r4, _DEAR(r11)

	li	r5,0			/* Pass zero as arg3 */

	EXC_XFER_LITE(0x400, handle_page_fault)
@@ -676,6 +677,7 @@ DataAccess: 
	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it, pass arg3 */

	stw	r5,_ESR(r11)

	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it, pass arg2 */

	stw	r4, _DEAR(r11)

	EXC_XFER_LITE(0x300, handle_page_fault)



/* Other PowerPC processors, namely those derived from the 6xx-series

arch/powerpc/kernel/head_8xx.S

+2 −0
Original line number Diff line number Diff line
@@ -486,6 +486,7 @@ InstructionTLBError: 
	tlbie	r4

	/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */

.Litlbie:

	stw	r4, _DAR(r11)

	EXC_XFER_LITE(0x400, handle_page_fault)



/* This is the data TLB error on the MPC8xx.  This could be due to
@@ -504,6 +505,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */ 
	mfspr	r5,SPRN_DSISR

	stw	r5,_DSISR(r11)

	mfspr	r4,SPRN_DAR

	stw	r4, _DAR(r11)

	andis.	r10,r5,DSISR_NOHPTE@h

	beq+	.Ldtlbie

	tlbie	r4

arch/powerpc/kernel/head_booke.h

+2 −0
Original line number Diff line number Diff line
@@ -467,6 +467,7 @@ label: 
	mfspr	r5,SPRN_ESR;		/* Grab the ESR and save it */	      \

	stw	r5,_ESR(r11);						      \

	mfspr	r4,SPRN_DEAR;		/* Grab the DEAR */		      \

	stw	r4, _DEAR(r11);						      \

	EXC_XFER_LITE(0x0300, handle_page_fault)



#define INSTRUCTION_STORAGE_EXCEPTION					      \
@@ -475,6 +476,7 @@ label: 
	mfspr	r5,SPRN_ESR;		/* Grab the ESR and save it */	      \

	stw	r5,_ESR(r11);						      \

	mr      r4,r12;                 /* Pass SRR0 as arg2 */		      \

	stw	r4, _DEAR(r11);						      \

	li      r5,0;                   /* Pass zero as arg3 */		      \

	EXC_XFER_LITE(0x0400, handle_page_fault)

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