Commit 1c994f2d authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: update dml interfaces and variables 



Preparation for new asic support.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fe593296

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

+1 −32
Original line number Diff line number Diff line
@@ -890,11 +890,6 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	double refcyc_per_req_delivery_c;



	unsigned int full_recout_width;

	double xfc_transfer_delay;

	double xfc_precharge_delay;

	double xfc_remote_surface_flip_latency;

	double xfc_dst_y_delta_drq_limit;

	double xfc_prefetch_margin;

	double refcyc_per_req_delivery_pre_cur0;

	double refcyc_per_req_delivery_cur0;

	double refcyc_per_req_delivery_pre_cur1;
@@ -1344,22 +1339,6 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

	}



	// XFC

	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);

	xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);

	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);

	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;

	xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);



	// TTU - Cursor

	refcyc_per_req_delivery_pre_cur0 = 0.0;

	refcyc_per_req_delivery_cur0 = 0.0;
@@ -1510,16 +1489,6 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;

	disp_dlg_regs->dst_y_offset_cur1 = 0;



	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;

	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;

	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;

	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,

			1);



	// slave has to have this value also set to off

	if (src->xfc_enable && !src->xfc_slave)

		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);

	else

	disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off



	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

+1 −32
Original line number Diff line number Diff line
@@ -890,11 +890,6 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	double refcyc_per_req_delivery_c;



	unsigned int full_recout_width;

	double xfc_transfer_delay;

	double xfc_precharge_delay;

	double xfc_remote_surface_flip_latency;

	double xfc_dst_y_delta_drq_limit;

	double xfc_prefetch_margin;

	double refcyc_per_req_delivery_pre_cur0;

	double refcyc_per_req_delivery_cur0;

	double refcyc_per_req_delivery_pre_cur1;
@@ -1345,22 +1340,6 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

	}



	// XFC

	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);

	xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);

	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);

	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;

	xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);



	// TTU - Cursor

	refcyc_per_req_delivery_pre_cur0 = 0.0;

	refcyc_per_req_delivery_cur0 = 0.0;
@@ -1511,16 +1490,6 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;

	disp_dlg_regs->dst_y_offset_cur1 = 0;



	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;

	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;

	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;

	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,

			1);



	// slave has to have this value also set to off

	if (src->xfc_enable && !src->xfc_slave)

		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);

	else

	disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off



	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

+1 −35
Original line number Diff line number Diff line
@@ -936,11 +936,6 @@ static void dml_rq_dlg_get_dlg_params( 
	double refcyc_per_req_delivery_c;



	unsigned int full_recout_width;

	double xfc_transfer_delay;

	double xfc_precharge_delay;

	double xfc_remote_surface_flip_latency;

	double xfc_dst_y_delta_drq_limit;

	double xfc_prefetch_margin;

	double refcyc_per_req_delivery_pre_cur0;

	double refcyc_per_req_delivery_cur0;

	double refcyc_per_req_delivery_pre_cur1;
@@ -1412,25 +1407,6 @@ static void dml_rq_dlg_get_dlg_params( 
		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

	}



	// XFC

	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);

	xfc_precharge_delay = get_xfc_precharge_delay(

			mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);

	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(

			mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);

	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;

	xfc_prefetch_margin = get_xfc_prefetch_margin(

			mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx);



	// TTU - Cursor

	refcyc_per_req_delivery_pre_cur0 = 0.0;

	refcyc_per_req_delivery_cur0 = 0.0;
@@ -1621,16 +1597,6 @@ static void dml_rq_dlg_get_dlg_params( 
	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;

	disp_dlg_regs->dst_y_offset_cur1 = 0;



	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;

	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;

	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;

	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(

			xfc_prefetch_margin * refclk_freq_in_mhz, 1);



	// slave has to have this value also set to off

	if (src->xfc_enable && !src->xfc_slave)

		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);

	else

	disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off



	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

+7 −1
Original line number Diff line number Diff line
@@ -177,8 +177,14 @@ enum odm_combine_policy { 
};



enum immediate_flip_requirement {

	dm_immediate_flip_not_required,

	dm_immediate_flip_required,

	dm_immediate_flip_not_required,

};



enum unbounded_requesting_policy {

	dm_unbounded_requesting,

	dm_unbounded_requesting_edp_only,

	dm_unbounded_requesting_disable

};



#endif

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

+11 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ struct _vcs_dpi_soc_bounding_box_st { 
	double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly

	double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;

	double pct_ideal_dram_sdp_bw_after_urgent_vm_only;

	double pct_ideal_sdp_bw_after_urgent;

	double max_avg_sdp_bw_use_normal_percent;

	double max_avg_dram_bw_use_normal_percent;

	unsigned int max_request_size_bytes;
@@ -125,6 +126,7 @@ struct _vcs_dpi_ip_params_st { 
	bool use_min_dcfclk;

	bool gpuvm_enable;

	bool hostvm_enable;

	bool dsc422_native_support;

	unsigned int gpuvm_max_page_table_levels;

	unsigned int hostvm_max_page_table_levels;

	unsigned int hostvm_cached_page_table_levels;
@@ -143,6 +145,7 @@ struct _vcs_dpi_ip_params_st { 
	unsigned char pte_enable;

	unsigned int pte_chunk_size_kbytes;

	unsigned int meta_chunk_size_kbytes;

	unsigned int min_meta_chunk_size_bytes;

	unsigned int writeback_chunk_size_kbytes;

	unsigned int line_buffer_size_bits;

	unsigned int max_line_buffer_lines;
@@ -158,6 +161,7 @@ struct _vcs_dpi_ip_params_st { 
	double writeback_max_vscl_ratio;

	double writeback_min_hscl_ratio;

	double writeback_min_vscl_ratio;

	double maximum_dsc_bits_per_component;

	unsigned int writeback_max_hscl_taps;

	unsigned int writeback_max_vscl_taps;

	unsigned int writeback_line_buffer_luma_buffer_size;
@@ -219,11 +223,14 @@ struct _vcs_dpi_display_xfc_params_st { 


struct _vcs_dpi_display_pipe_source_params_st {

	int source_format;

	double dcc_fraction_of_zs_req_luma;

	double dcc_fraction_of_zs_req_chroma;

	unsigned char dcc;

	unsigned int dcc_rate;

	unsigned int dcc_rate_chroma;

	unsigned char dcc_use_global;

	unsigned char vm;

	bool unbounded_req_mode;

	bool gpuvm;    // gpuvm enabled

	bool hostvm;    // hostvm enabled

	bool gpuvm_levels_force_en;
@@ -324,6 +331,8 @@ struct _vcs_dpi_display_pipe_dest_params_st { 
	unsigned int vblank_end;

	unsigned int htotal;

	unsigned int vtotal;

	unsigned int refresh_rate;

	unsigned int vfront_porch;

	unsigned int vactive;

	unsigned int hactive;

	unsigned int vstartup_start;
@@ -333,6 +342,7 @@ struct _vcs_dpi_display_pipe_dest_params_st { 
	unsigned char interlaced;

	double pixel_rate_mhz;

	unsigned char synchronized_vblank_all_planes;

	unsigned char synchronize_timing_if_single_refresh_rate;

	unsigned char otg_inst;

	unsigned int odm_combine;

	unsigned char use_maximum_vstartup;
@@ -469,6 +479,7 @@ struct _vcs_dpi_display_dlg_regs_st { 
	unsigned int refcyc_per_vm_req_vblank;

	unsigned int refcyc_per_vm_req_flip;

	unsigned int refcyc_per_vm_dmdata;

	unsigned int dmdata_dl_delta;

};



struct _vcs_dpi_display_ttu_regs_st {

CRA Git | Maintained and supported by SUSTech CRA and CCSE