Commit 1c8e6004 authored by Tomeu Vizoso's avatar Tomeu Vizoso Committed by Michael Turquette
Browse files

clk: Add rate constraints to clocks 



Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.

Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.

Signed-off-by: default avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                        migrated clk-private.h changes to clk.c]
parent b09d6d99

Documentation/clk.txt

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ the operations defined in clk.h: 
						unsigned long *parent_rate);

		long		(*determine_rate)(struct clk_hw *hw,

						unsigned long rate,

						unsigned long min_rate,

						unsigned long max_rate,

						unsigned long *best_parent_rate,

						struct clk_hw **best_parent_clk);

		int		(*set_parent)(struct clk_hw *hw, u8 index);

arch/arm/mach-omap2/dpll3xxx.c

+2 −0
Original line number Diff line number Diff line
@@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) 
 * in failure.

 */

long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,

				       unsigned long min_rate,

				       unsigned long max_rate,

				       unsigned long *best_parent_rate,

				       struct clk_hw **best_parent_clk)

{

arch/arm/mach-omap2/dpll44xx.c

+2 −0
Original line number Diff line number Diff line
@@ -222,6 +222,8 @@ out: 
 * in failure.

 */

long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,

					unsigned long min_rate,

					unsigned long max_rate,

					unsigned long *best_parent_rate,

					struct clk_hw **best_parent_clk)

{

arch/mips/alchemy/common/clock.c

+8 −0
Original line number Diff line number Diff line
@@ -373,6 +373,8 @@ static long alchemy_calc_div(unsigned long rate, unsigned long prate, 
}



static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,

					unsigned long min_rate,

					unsigned long max_rate,

					unsigned long *best_parent_rate,

					struct clk_hw **best_parent_clk,

					int scale, int maxdiv)
@@ -546,6 +548,8 @@ static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw, 
}



static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,

					unsigned long min_rate,

					unsigned long max_rate,

					unsigned long *best_parent_rate,

					struct clk_hw **best_parent_clk)

{
@@ -678,6 +682,8 @@ static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw, 
}



static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,

					unsigned long min_rate,

					unsigned long max_rate,

					unsigned long *best_parent_rate,

					struct clk_hw **best_parent_clk)

{
@@ -897,6 +903,8 @@ static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate, 
}



static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,

					unsigned long min_rate,

					unsigned long max_rate,

					unsigned long *best_parent_rate,

					struct clk_hw **best_parent_clk)

{

drivers/clk/at91/clk-programmable.c

+2 −0
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, 


static long clk_programmable_determine_rate(struct clk_hw *hw,

					    unsigned long rate,

					    unsigned long min_rate,

					    unsigned long max_rate,

					    unsigned long *best_parent_rate,

					    struct clk_hw **best_parent_hw)

{

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