Commit 1c8d2969 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'io' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into asm-generic 

* 'io' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux

:
  documentation: memory-barriers: clarify relaxed io accessor semantics
  x86: io: implement dummy relaxed accessor macros for writes
  tile: io: implement dummy relaxed accessor macros for writes
  sparc: io: implement dummy relaxed accessor macros for writes
  powerpc: io: implement dummy relaxed accessor macros for writes
  parisc: io: implement dummy relaxed accessor macros for writes
  mn10300: io: implement dummy relaxed accessor macros for writes
  m68k: io: implement dummy relaxed accessor macros for writes
  m32r: io: implement dummy relaxed accessor macros for writes
  ia64: io: implement dummy relaxed accessor macros for writes
  cris: io: implement dummy relaxed accessor macros for writes
  frv: io: implement dummy relaxed accessor macros for writes
  xtensa: io: remove dummy relaxed accessor macros for reads
  s390: io: remove dummy relaxed accessor macros for reads
  microblaze: io: remove dummy relaxed accessor macros
  asm-generic: io: implement relaxed accessor macros as conditional wrappers

Conflicts:
	include/asm-generic/io.h

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3ba5acf3 a8e0aead

Documentation/memory-barriers.txt

+9 −4
Original line number Diff line number Diff line
@@ -2465,10 +2465,15 @@ functions: 
     Please refer to the PCI specification for more information on interactions

     between PCI transactions.



 (*) readX_relaxed()



     These are similar to readX(), but are not guaranteed to be ordered in any

     way. Be aware that there is no I/O read barrier available.

 (*) readX_relaxed(), writeX_relaxed()



     These are similar to readX() and writeX(), but provide weaker memory

     ordering guarantees. Specifically, they do not guarantee ordering with

     respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee

     ordering with respect to LOCK or UNLOCK operations. If the latter is

     required, an mmiowb() barrier can be used. Note that relaxed accesses to

     the same peripheral are guaranteed to be ordered with respect to each

     other.



 (*) ioreadX(), iowriteX()

arch/cris/include/asm/io.h

+3 −0
Original line number Diff line number Diff line
@@ -112,6 +112,9 @@ static inline void writel(unsigned int b, volatile void __iomem *addr) 
	else

		*(volatile unsigned int __force *) addr = b;

}

#define writeb_relaxed(b, addr) writeb(b, addr)

#define writew_relaxed(b, addr) writew(b, addr)

#define writel_relaxed(b, addr) writel(b, addr)

#define __raw_writeb writeb

#define __raw_writew writew

#define __raw_writel writel

arch/frv/include/asm/io.h

+3 −0
Original line number Diff line number Diff line
@@ -243,6 +243,9 @@ static inline void writel(uint32_t datum, volatile void __iomem *addr) 
		__flush_PCI_writes();

}



#define writeb_relaxed writeb

#define writew_relaxed writew

#define writel_relaxed writel



/* Values for nocacheflag and cmode */

#define IOMAP_FULL_CACHING		0

arch/ia64/include/asm/io.h

+4 −0
Original line number Diff line number Diff line
@@ -393,6 +393,10 @@ __writeq (unsigned long val, volatile void __iomem *addr) 
#define writew(v,a)	__writew((v), (a))

#define writel(v,a)	__writel((v), (a))

#define writeq(v,a)	__writeq((v), (a))

#define writeb_relaxed(v,a)	__writeb((v), (a))

#define writew_relaxed(v,a)	__writew((v), (a))

#define writel_relaxed(v,a)	__writel((v), (a))

#define writeq_relaxed(v,a)	__writeq((v), (a))

#define __raw_writeb	writeb

#define __raw_writew	writew

#define __raw_writel	writel

arch/m32r/include/asm/io.h

+3 −0
Original line number Diff line number Diff line
@@ -161,6 +161,9 @@ static inline void _writel(unsigned long l, unsigned long addr) 
#define __raw_writeb writeb

#define __raw_writew writew

#define __raw_writel writel

#define writeb_relaxed writeb

#define writew_relaxed writew

#define writel_relaxed writel



#define ioread8 read

#define ioread16 readw

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