Commit 1c839141 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
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arm64/cpufeatures: Introduce ESR_ELx_SYS64_ISS_RT() 



Extracting target register from ESR.ISS encoding has already been required
at multiple instances. Just make it a macro definition and replace all the
existing use cases.

Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 880f7cc4

arch/arm64/include/asm/esr.h

+2 −0
Original line number Diff line number Diff line
@@ -187,6 +187,8 @@ 


#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \

					 ESR_ELx_SYS64_ISS_DIR_MASK)

#define ESR_ELx_SYS64_ISS_RT(esr) \

	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)

/*

 * User space cache operations have the following sysreg encoding

 * in System instructions.

arch/arm64/include/asm/kvm_emulate.h

+1 −1
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu) 
static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)

{

	u32 esr = kvm_vcpu_get_hsr(vcpu);

	return (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;

	return ESR_ELx_SYS64_ISS_RT(esr);

}



static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)

arch/arm64/kernel/traps.c

+4 −4
Original line number Diff line number Diff line
@@ -438,7 +438,7 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) 
static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)

{

	unsigned long address;

	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;

	int rt = ESR_ELx_SYS64_ISS_RT(esr);

	int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;

	int ret = 0;
@@ -473,7 +473,7 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 


static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)

{

	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;

	int rt = ESR_ELx_SYS64_ISS_RT(esr);

	unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);



	pt_regs_write_reg(regs, rt, val);
@@ -483,7 +483,7 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) 


static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)

{

	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;

	int rt = ESR_ELx_SYS64_ISS_RT(esr);



	pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());

	arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
@@ -491,7 +491,7 @@ static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 


static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)

{

	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;

	int rt = ESR_ELx_SYS64_ISS_RT(esr);



	pt_regs_write_reg(regs, rt, arch_timer_get_rate());

	arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);

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