Commit 1c80f4b5 authored May 15, 2009 by Ingo Molnar

perf_counter: x86: Disallow interval of 1



On certain CPUs i have observed a stuck PMU if interval was set to
1 and NMIs were used. The PMU had PMC0 set in MSR_CORE_PERF_GLOBAL_STATUS,
but it was not possible to ack it via MSR_CORE_PERF_GLOBAL_OVF_CTRL,
and the NMI loop got stuck infinitely.

[ Impact: fix rare hangs during high perfcounter load ]

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

parent a4016a79

arch/x86/kernel/cpu/perf_counter.c

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -473,6 +473,11 @@ x86_perf_counter_set_period(struct perf_counter *counter,
	left += period;		left += period;
	atomic64_set(&hwc->period_left, left);		atomic64_set(&hwc->period_left, left);
	}		}
			/*
			* Quirk: certain CPUs dont like it if just 1 event is left:
			*/
			if (unlikely(left < 2))
			left = 2;

	per_cpu(prev_left[idx], smp_processor_id()) = left;		per_cpu(prev_left[idx], smp_processor_id()) = left;

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