drm/i915/tgl: Implement Wa_1409142259 (1c757497) · Commits · 戴 / test

Disable CPS aware color pipe by setting chicken bit. BSpec: 52890 HSDES: 1409142259 v2: Move WA to ctx WA's(Daniele) Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Stuart Summers <stuart.summers@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:

Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:

Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190909231445.23815-1-radhakrishna.sripada@intel.com Reviewed-by:

Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -567,6 +567,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
		static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
		struct i915_wa_list *wal)
		{
		/* Wa_1409142259 */
		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
		GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
		}

		static void

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -7672,6 +7672,7 @@ enum {

		#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
		#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
		#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)

		#define HIZ_CHICKEN _MMIO(0x7018)
		# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)

Admin message