Commit 1c5ff0f5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6 

* 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6:
  gpio: Fix DA9052 GPIO build errors.
  gpio: mpc8xxx: don't allow input-only pins to be output for MPC5121
  gpio-ml-ioh: Add the irq_disable/irq_enable hooks for ml-ioh irq chip
  gpio-ml-ioh: fix a bug in the interrupt handler
  gpio: pl061: drop extra check for NULL platform_data
parents 3f5fcf60 87b9b0e0

drivers/gpio/gpio-da9052.c

+8 −13
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
#include <linux/mfd/da9052/da9052.h>

#include <linux/mfd/da9052/reg.h>

#include <linux/mfd/da9052/pdata.h>

#include <linux/mfd/da9052/gpio.h>



#define DA9052_INPUT				1

#define DA9052_OUTPUT_OPENDRAIN		2
@@ -43,6 +42,9 @@ 
#define DA9052_GPIO_MASK_UPPER_NIBBLE		0xF0

#define DA9052_GPIO_MASK_LOWER_NIBBLE		0x0F

#define DA9052_GPIO_NIBBLE_SHIFT		4

#define DA9052_IRQ_GPI0			16

#define DA9052_GPIO_ODD_SHIFT			7

#define DA9052_GPIO_EVEN_SHIFT			3



struct da9052_gpio {

	struct da9052 *da9052;
@@ -104,35 +106,28 @@ static int da9052_gpio_get(struct gpio_chip *gc, unsigned offset) 
static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)

{

	struct da9052_gpio *gpio = to_da9052_gpio(gc);

	unsigned char register_value = 0;

	int ret;



	if (da9052_gpio_port_odd(offset)) {

		if (value) {

			register_value = DA9052_GPIO_ODD_PORT_MODE;

			ret = da9052_reg_update(gpio->da9052, (offset >> 1) +

						DA9052_GPIO_0_1_REG,

						DA9052_GPIO_ODD_PORT_MODE,

						register_value);

						value << DA9052_GPIO_ODD_SHIFT);

			if (ret != 0)

				dev_err(gpio->da9052->dev,

					"Failed to updated gpio odd reg,%d",

					ret);

		}

	} else {

		if (value) {

			register_value = DA9052_GPIO_EVEN_PORT_MODE;

			ret = da9052_reg_update(gpio->da9052, (offset >> 1) +

						DA9052_GPIO_0_1_REG,

						DA9052_GPIO_EVEN_PORT_MODE,

						register_value);

						value << DA9052_GPIO_EVEN_SHIFT);

			if (ret != 0)

				dev_err(gpio->da9052->dev,

					"Failed to updated gpio even reg,%d",

					ret);

	}

}

}



static int da9052_gpio_direction_input(struct gpio_chip *gc, unsigned offset)

{
@@ -201,9 +196,9 @@ static struct gpio_chip reference_gp __devinitdata = { 
	.direction_input = da9052_gpio_direction_input,

	.direction_output = da9052_gpio_direction_output,

	.to_irq = da9052_gpio_to_irq,

	.can_sleep = 1;

	.ngpio = 16;

	.base = -1;

	.can_sleep = 1,

	.ngpio = 16,

	.base = -1,

};



static int __devinit da9052_gpio_probe(struct platform_device *pdev)

drivers/gpio/gpio-ml-ioh.c

+31 −1
Original line number Diff line number Diff line
@@ -332,6 +332,34 @@ static void ioh_irq_mask(struct irq_data *d) 
		  &chip->reg->regs[chip->ch].imask);

}



static void ioh_irq_disable(struct irq_data *d)

{

	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	struct ioh_gpio *chip = gc->private;

	unsigned long flags;

	u32 ien;



	spin_lock_irqsave(&chip->spinlock, flags);

	ien = ioread32(&chip->reg->regs[chip->ch].ien);

	ien &= ~(1 << (d->irq - chip->irq_base));

	iowrite32(ien, &chip->reg->regs[chip->ch].ien);

	spin_unlock_irqrestore(&chip->spinlock, flags);

}



static void ioh_irq_enable(struct irq_data *d)

{

	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	struct ioh_gpio *chip = gc->private;

	unsigned long flags;

	u32 ien;



	spin_lock_irqsave(&chip->spinlock, flags);

	ien = ioread32(&chip->reg->regs[chip->ch].ien);

	ien |= 1 << (d->irq - chip->irq_base);

	iowrite32(ien, &chip->reg->regs[chip->ch].ien);

	spin_unlock_irqrestore(&chip->spinlock, flags);

}



static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)

{

	struct ioh_gpio *chip = dev_id;
@@ -339,7 +367,7 @@ static irqreturn_t ioh_gpio_handler(int irq, void *dev_id) 
	int i, j;

	int ret = IRQ_NONE;



	for (i = 0; i < 8; i++) {

	for (i = 0; i < 8; i++, chip++) {

		reg_val = ioread32(&chip->reg->regs[i].istatus);

		for (j = 0; j < num_ports[i]; j++) {

			if (reg_val & BIT(j)) {
@@ -370,6 +398,8 @@ static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip, 
	ct->chip.irq_mask = ioh_irq_mask;

	ct->chip.irq_unmask = ioh_irq_unmask;

	ct->chip.irq_set_type = ioh_irq_type;

	ct->chip.irq_disable = ioh_irq_disable;

	ct->chip.irq_enable = ioh_irq_enable;



	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,

			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);

drivers/gpio/gpio-mpc8xxx.c

+13 −5
Original line number Diff line number Diff line
@@ -132,6 +132,15 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val 
	return 0;

}



static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)

{

	/* GPIO 28..31 are input only on MPC5121 */

	if (gpio >= 28)

		return -EINVAL;



	return mpc8xxx_gpio_dir_out(gc, gpio, val);

}



static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)

{

	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
@@ -340,11 +349,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np) 
	mm_gc->save_regs = mpc8xxx_gpio_save_regs;

	gc->ngpio = MPC8XXX_GPIO_PINS;

	gc->direction_input = mpc8xxx_gpio_dir_in;

	gc->direction_output = mpc8xxx_gpio_dir_out;

	if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))

		gc->get = mpc8572_gpio_get;

	else

		gc->get = mpc8xxx_gpio_get;

	gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?

		mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;

	gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?

		mpc8572_gpio_get : mpc8xxx_gpio_get;

	gc->set = mpc8xxx_gpio_set;

	gc->to_irq = mpc8xxx_gpio_to_irq;

drivers/gpio/gpio-pl061.c

+0 −4
Original line number Diff line number Diff line
@@ -238,10 +238,6 @@ static int pl061_probe(struct amba_device *dev, const struct amba_id *id) 
	int ret, irq, i;

	static DECLARE_BITMAP(init_irq, NR_IRQS);



	pdata = dev->dev.platform_data;

	if (pdata == NULL)

		return -ENODEV;



	chip = kzalloc(sizeof(*chip), GFP_KERNEL);

	if (chip == NULL)

		return -ENOMEM;

CRA Git | Maintained and supported by SUSTech CRA and CCSE