drm/amd/display: enable S/G for RAVEN chip (1c425915) · Commits · 戴 / test

enables gpu_vm_support in dm and adds AMDGPU_GEM_DOMAIN_GTT as supported domain v2: Move BO placement logic into amdgpu_display_supported_domains v3: Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains. v4: amdgpu_bo_validate_uswc moved to sepperate patch. Signed-off-by:

Shirish S <shirish.s@amd.com> Signed-off-by:

Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:

Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -507,7 +507,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
		* APUs. So force the BO placement to VRAM in case this architecture
		* will not allow USWC mappings.
		*/
		if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
		if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
		adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) &&
		amdgpu_device_asic_has_dc_support(adev->asic_type))
		domain \|= AMDGPU_GEM_DOMAIN_GTT;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -688,7 +688,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
		*/
		if (adev->flags & AMD_IS_APU &&
		adev->asic_type >= CHIP_CARRIZO &&
		adev->asic_type < CHIP_RAVEN)
		adev->asic_type <= CHIP_RAVEN)
		init_data.flags.gpu_vm_support = true;

		if (amdgpu_dc_feature_mask & DC_FBC_MASK)

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