Commit 1c312e84 authored by Mark Rutland's avatar Mark Rutland Committed by Will Deacon
Browse files

arm64: move SCTLR_EL{1,2} assertions to <asm/sysreg.h> 



Currently we assert that the SCTLR_EL{1,2}_{SET,CLEAR} bits are
self-consistent with an assertion in config_sctlr_el1(). This is a bit
unusual, since config_sctlr_el1() doesn't make use of these definitions,
and is far away from the definitions themselves.

We can use the CPP #error directive to have equivalent assertions in
<asm/sysreg.h>, next to the definitions of the set/clear bits, which is
a bit clearer and simpler.

At the same time, lets fill in the upper 32 bits for both registers in
their respective RES0 definitions. This could be a little nicer with
GENMASK_ULL(63, 32), but this currently lives in <linux/bitops.h>, which
cannot safely be included from assembly, as <asm/sysreg.h> can.

Note the when the preprocessor evaluates an expression for an #if
directive, all signed or unsigned values are treated as intmax_t or
uintmax_t respectively. To avoid ambiguity, we define explicitly define
the mask of all 64 bits.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Cc: Dave Martin <dave.martin@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 3eb6f1f9

arch/arm64/include/asm/sysreg.h

+10 −10
Original line number Diff line number Diff line
@@ -436,7 +436,8 @@ 
#define SCTLR_EL2_RES0	((1 << 6)  | (1 << 7)  | (1 << 8)  | (1 << 9)  | \

			 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \

			 (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \

			 (1 << 27) | (1 << 30) | (1 << 31))

			 (1 << 27) | (1 << 30) | (1 << 31) | \

			 (0xffffffffUL << 32))



#ifdef CONFIG_CPU_BIG_ENDIAN

#define ENDIAN_SET_EL2		SCTLR_ELx_EE
@@ -452,9 +453,9 @@ 
			 SCTLR_ELx_SA     | SCTLR_ELx_I    | SCTLR_ELx_WXN | \

			 ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)



/* Check all the bits are accounted for */

#define SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS	BUILD_BUG_ON((SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != ~0)



#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff

#error "Inconsistent SCTLR_EL2 set/clear bits"

#endif



/* SCTLR_EL1 specific flags. */

#define SCTLR_EL1_UCI		(1 << 26)
@@ -473,7 +474,8 @@ 
#define SCTLR_EL1_RES1	((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \

			 (1 << 29))

#define SCTLR_EL1_RES0  ((1 << 6)  | (1 << 10) | (1 << 13) | (1 << 17) | \

			 (1 << 27) | (1 << 30) | (1 << 31))

			 (1 << 27) | (1 << 30) | (1 << 31) | \

			 (0xffffffffUL << 32))



#ifdef CONFIG_CPU_BIG_ENDIAN

#define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
@@ -492,8 +494,9 @@ 
			 SCTLR_EL1_UMA | SCTLR_ELx_WXN     | ENDIAN_CLEAR_EL1 |\

			 SCTLR_EL1_RES0)



/* Check all the bits are accounted for */

#define SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS	BUILD_BUG_ON((SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != ~0)

#if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff

#error "Inconsistent SCTLR_EL1 set/clear bits"

#endif



/* id_aa64isar0 */

#define ID_AA64ISAR0_TS_SHIFT		52
@@ -743,9 +746,6 @@ static inline void config_sctlr_el1(u32 clear, u32 set) 
{

	u32 val;



	SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS;

	SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS;



	val = read_sysreg(sctlr_el1);

	val &= ~clear;

	val |= set;

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