powerpc/mm: Refactor pte_update() on book3s/32

 * and the PTE may be either 32 or 64 bit wide. In the later case,

 * when using atomic updates, only the low part of the PTE is

 * accessed atomically.

 *

 * In addition, on 44x, we also maintain a global flag indicating

 * that an executable user mapping was modified, which is needed

 * to properly flush the virtually tagged instruction cache of

 * those implementations.

 */

#ifndef CONFIG_PTE_64BIT

static inline unsigned long pte_update(pte_t *p,

				       unsigned long clr,

				       unsigned long set)

static inline pte_basic_t pte_update(pte_t *p, unsigned long clr, unsigned long set)

{

	unsigned long old, tmp;

	__asm__ __volatile__("\

1:	lwarx	%0,0,%3\n\

	andc	%1,%0,%4\n\

	or	%1,%1,%5\n"

"	stwcx.	%1,0,%3\n\

	bne-	1b"

	: "=&r" (old), "=&r" (tmp), "=m" (*p)

	: "r" (p), "r" (clr), "r" (set), "m" (*p)

	: "cc" );

	return old;

}

#else /* CONFIG_PTE_64BIT */

static inline unsigned long long pte_update(pte_t *p,

					    unsigned long clr,

					    unsigned long set)

{

	unsigned long long old;

	pte_basic_t old;

	unsigned long tmp;

	__asm__ __volatile__("\

1:	lwarx	%L0,0,%4\n\

	lwzx	%0,0,%3\n\

	andc	%1,%L0,%5\n\

	or	%1,%1,%6\n"

"	stwcx.	%1,0,%4\n\

	bne-	1b"

	__asm__ __volatile__(

#ifndef CONFIG_PTE_64BIT

"1:	lwarx	%0, 0, %3\n"

"	andc	%1, %0, %4\n"

#else

"1:	lwarx	%L0, 0, %3\n"

"	lwz	%0, -4(%3)\n"

"	andc	%1, %L0, %4\n"

#endif

"	or	%1, %1, %5\n"

"	stwcx.	%1, 0, %3\n"

"	bne-	1b"

	: "=&r" (old), "=&r" (tmp), "=m" (*p)

	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)

#ifndef CONFIG_PTE_64BIT

	: "r" (p),

#else

	: "b" ((unsigned long)(p) + 4),

#endif

	  "r" (clr), "r" (set), "m" (*p)

	: "cc" );

	return old;

}

#endif /* CONFIG_PTE_64BIT */

/*

 * 2.6 calls this without flushing the TLB entry; this is wrong