Commit 1c101da8 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

arm64: mte: Allow user control of the tag check mode via prctl() 



By default, even if PROT_MTE is set on a memory range, there is no tag
check fault reporting (SIGSEGV). Introduce a set of option to the
exiting prctl(PR_SET_TAGGED_ADDR_CTRL) to allow user control of the tag
check fault mode:

  PR_MTE_TCF_NONE  - no reporting (default)
  PR_MTE_TCF_SYNC  - synchronous tag check fault reporting
  PR_MTE_TCF_ASYNC - asynchronous tag check fault reporting

These options translate into the corresponding SCTLR_EL1.TCF0 bitfield,
context-switched by the kernel. Note that the kernel accesses to the
user address space (e.g. read() system call) are not checked if the user
thread tag checking mode is PR_MTE_TCF_NONE or PR_MTE_TCF_ASYNC. If the
tag checking mode is PR_MTE_TCF_SYNC, the kernel makes a best effort to
check its user address accesses, however it cannot always guarantee it.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
parent 51b0bff2

arch/arm64/include/asm/mte.h

+14 −0
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ void mte_clear_page_tags(void *addr); 
void mte_sync_tags(pte_t *ptep, pte_t pte);

void mte_copy_page_tags(void *kto, const void *kfrom);

void flush_mte_state(void);

void mte_thread_switch(struct task_struct *next);

long set_mte_ctrl(unsigned long arg);

long get_mte_ctrl(void);



#else
@@ -36,6 +39,17 @@ static inline void mte_copy_page_tags(void *kto, const void *kfrom) 
static inline void flush_mte_state(void)

{

}

static inline void mte_thread_switch(struct task_struct *next)

{

}

static inline long set_mte_ctrl(unsigned long arg)

{

	return 0;

}

static inline long get_mte_ctrl(void)

{

	return 0;

}



#endif

arch/arm64/include/asm/processor.h

+3 −0
Original line number Diff line number Diff line
@@ -151,6 +151,9 @@ struct thread_struct { 
	struct ptrauth_keys_user	keys_user;

	struct ptrauth_keys_kernel	keys_kernel;

#endif

#ifdef CONFIG_ARM64_MTE

	u64			sctlr_tcf0;

#endif

};



static inline void arch_thread_struct_whitelist(unsigned long *offset,

arch/arm64/kernel/mte.c

+77 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 


#include <linux/bitops.h>

#include <linux/mm.h>

#include <linux/prctl.h>

#include <linux/sched.h>

#include <linux/string.h>

#include <linux/thread_info.h>
@@ -49,6 +51,26 @@ int memcmp_pages(struct page *page1, struct page *page2) 
	return ret;

}



static void update_sctlr_el1_tcf0(u64 tcf0)

{

	/* ISB required for the kernel uaccess routines */

	sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF0_MASK, tcf0);

	isb();

}



static void set_sctlr_el1_tcf0(u64 tcf0)

{

	/*

	 * mte_thread_switch() checks current->thread.sctlr_tcf0 as an

	 * optimisation. Disable preemption so that it does not see

	 * the variable update before the SCTLR_EL1.TCF0 one.

	 */

	preempt_disable();

	current->thread.sctlr_tcf0 = tcf0;

	update_sctlr_el1_tcf0(tcf0);

	preempt_enable();

}



void flush_mte_state(void)

{

	if (!system_supports_mte())
@@ -58,4 +80,59 @@ void flush_mte_state(void) 
	dsb(ish);

	write_sysreg_s(0, SYS_TFSRE0_EL1);

	clear_thread_flag(TIF_MTE_ASYNC_FAULT);

	/* disable tag checking */

	set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE);

}



void mte_thread_switch(struct task_struct *next)

{

	if (!system_supports_mte())

		return;



	/* avoid expensive SCTLR_EL1 accesses if no change */

	if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0)

		update_sctlr_el1_tcf0(next->thread.sctlr_tcf0);

}



long set_mte_ctrl(unsigned long arg)

{

	u64 tcf0;



	if (!system_supports_mte())

		return 0;



	switch (arg & PR_MTE_TCF_MASK) {

	case PR_MTE_TCF_NONE:

		tcf0 = SCTLR_EL1_TCF0_NONE;

		break;

	case PR_MTE_TCF_SYNC:

		tcf0 = SCTLR_EL1_TCF0_SYNC;

		break;

	case PR_MTE_TCF_ASYNC:

		tcf0 = SCTLR_EL1_TCF0_ASYNC;

		break;

	default:

		return -EINVAL;

	}



	set_sctlr_el1_tcf0(tcf0);



	return 0;

}



long get_mte_ctrl(void)

{

	if (!system_supports_mte())

		return 0;



	switch (current->thread.sctlr_tcf0) {

	case SCTLR_EL1_TCF0_NONE:

		return PR_MTE_TCF_NONE;

	case SCTLR_EL1_TCF0_SYNC:

		return PR_MTE_TCF_SYNC;

	case SCTLR_EL1_TCF0_ASYNC:

		return PR_MTE_TCF_ASYNC;

	}



	return 0;

}

arch/arm64/kernel/process.c

+23 −3
Original line number Diff line number Diff line
@@ -577,6 +577,13 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, 
	 */

	dsb(ish);



	/*

	 * MTE thread switching must happen after the DSB above to ensure that

	 * any asynchronous tag check faults have been logged in the TFSR*_EL1

	 * registers.

	 */

	mte_thread_switch(next);



	/* the actual thread switch */

	last = cpu_switch_to(prev, next);
@@ -636,9 +643,15 @@ static unsigned int tagged_addr_disabled; 


long set_tagged_addr_ctrl(unsigned long arg)

{

	unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;



	if (is_compat_task())

		return -EINVAL;

	if (arg & ~PR_TAGGED_ADDR_ENABLE)



	if (system_supports_mte())

		valid_mask |= PR_MTE_TCF_MASK;



	if (arg & ~valid_mask)

		return -EINVAL;



	/*
@@ -648,6 +661,9 @@ long set_tagged_addr_ctrl(unsigned long arg) 
	if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)

		return -EINVAL;



	if (set_mte_ctrl(arg) != 0)

		return -EINVAL;



	update_thread_flag(TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);



	return 0;
@@ -655,13 +671,17 @@ long set_tagged_addr_ctrl(unsigned long arg) 


long get_tagged_addr_ctrl(void)

{

	long ret = 0;



	if (is_compat_task())

		return -EINVAL;



	if (test_thread_flag(TIF_TAGGED_ADDR))

		return PR_TAGGED_ADDR_ENABLE;

		ret = PR_TAGGED_ADDR_ENABLE;



	return 0;

	ret |= get_mte_ctrl();



	return ret;

}



/*

include/uapi/linux/prctl.h

+6 −0
Original line number Diff line number Diff line
@@ -233,6 +233,12 @@ struct prctl_mm_map { 
#define PR_SET_TAGGED_ADDR_CTRL		55

#define PR_GET_TAGGED_ADDR_CTRL		56

# define PR_TAGGED_ADDR_ENABLE		(1UL << 0)

/* MTE tag check fault modes */

# define PR_MTE_TCF_SHIFT		1

# define PR_MTE_TCF_NONE		(0UL << PR_MTE_TCF_SHIFT)

# define PR_MTE_TCF_SYNC		(1UL << PR_MTE_TCF_SHIFT)

# define PR_MTE_TCF_ASYNC		(2UL << PR_MTE_TCF_SHIFT)

# define PR_MTE_TCF_MASK		(3UL << PR_MTE_TCF_SHIFT)



/* Control reclaim behavior when allocating memory */

#define PR_SET_IO_FLUSHER		57

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