Blackfin arch: add TXDWA definition to enable new feature

#define ANOMALY_05000245 (1)

/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */

#define ANOMALY_05000265 (1)

/* New Feature: EMAC TX DMA Word Alignment */

#define ANOMALY_05000285 (1)

/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */

#define ANOMALY_05000312 (1)

/* Incorrect Access of OTP_STATUS During otp_write() Function */

#define	PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */

#define	RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */

#define	RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */

#define	TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */

#define	MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */

#define	SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */

#define	PHYIE		0x00000001	/* PHY_INT Interrupt Enable                                                     */

#define	RXDWA		0x00000002	/* Receive Frame DMA Word Alignment (Odd/Even*)         */

#define	RXCKS		0x00000004	/* Enable RX Frame TCP/UDP Checksum Computation         */

#define	TXDWA		0x00000010	/* Transmit Frame DMA Word Alignment (Odd/Even*)        */

#define	MDCDIV		0x00003F00	/* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]          */

#define	SET_MDCDIV(x)	(((x)&0x3F)<< 8)	/* Set MDC Clock Divisor                                */