Commit 1be08f45 authored Sep 30, 2019 by Robin Murphy Committed by Will Deacon Oct 01, 2019

iommu/io-pgtable-arm: Support all Mali configurations



In principle, Midgard GPUs supporting smaller VA sizes should only
require 3-level pagetables, since level 0 only resolves bits 48:40 of
the address. However, the kbase driver does not appear to have any
notion of a variable start level, and empirically T720 and T820 rapidly
blow up with translation faults unless given a full 4-level table,
despite only supporting a 33-bit VA size.

The 'real' IAS value is still valuable in terms of validating addresses
on map/unmap, so tweak the allocator to allow smaller values while still
forcing the resultant tables to the full 4 levels. As far as I can test,
this should make all known Midgard variants happy.

Fixes: d08d42de ("iommu: io-pgtable: Add ARM Mali midgard MMU page table format")
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>

parent 52f325f4

drivers/iommu/io-pgtable-arm.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -1024,7 +1024,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg cfg, void cookie)
		if (cfg->quirks)
		return NULL;

		if (cfg->ias != 48 \|\| cfg->oas > 40)
		if (cfg->ias > 48 \|\| cfg->oas > 40)
		return NULL;

		cfg->pgsize_bitmap &= (SZ_4K \| SZ_2M \| SZ_1G);
		@@ -1033,6 +1033,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg cfg, void cookie)
		if (!data)
		return NULL;

		/* Mali seems to need a full 4-level table regardless of IAS */
		if (data->levels < ARM_LPAE_MAX_LEVELS) {
		data->levels = ARM_LPAE_MAX_LEVELS;
		data->pgd_size = sizeof(arm_lpae_iopte);
		}
		/*
		* MEMATTR: Mali has no actual notion of a non-cacheable type, so the
		* best we can do is mimic the out-of-tree driver and hope that the

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