Commit 1bcdc68d authored by Mike Rapoport's avatar Mike Rapoport Committed by Linus Torvalds
Browse files

m68k/mm: move {cache,nocahe}_page() definitions close to their user 



The cache_page() and nocache_page() functions are only used by the
motorola MMU variant for setting caching attributes for the page table
pages.

Move the definitions of these functions from
arch/m68k/include/asm/motorola_pgtable.h closer to their usage in
arch/m68k/mm/motorola.c and drop unused definition in
arch/m68k/include/asm/mcf_pgtable.h.

Signed-off-by: default avatarMike Rapoport <rppt@linux.ibm.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Acked-by: default avatarGreg Ungerer <gerg@linux-m68k.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Cain <bcain@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Greentime Hu <green.hu@gmail.com>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: Guo Ren <guoren@kernel.org>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Helge Deller <deller@gmx.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Mark Salter <msalter@redhat.com>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Nick Hu <nickhu@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Rich Felker <dalias@libc.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Stafford Horne <shorne@gmail.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vincent Chen <deanbo422@gmail.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Link: http://lkml.kernel.org/r/20200514170327.31389-7-rppt@kernel.org


Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent e73240be

arch/m68k/include/asm/mcf_pgtable.h

+0 −40
Original line number Diff line number Diff line
@@ -328,46 +328,6 @@ extern pgd_t kernel_pg_dir[PTRS_PER_PGD]; 
#define pte_offset_kernel(dir, address) \

	((pte_t *) __pmd_page(*(dir)) + __pte_offset(address))



/*

 * Disable caching for page at given kernel virtual address.

 */

static inline void nocache_page(void *vaddr)

{

	pgd_t *dir;

	p4d_t *p4dp;

	pud_t *pudp;

	pmd_t *pmdp;

	pte_t *ptep;

	unsigned long addr = (unsigned long) vaddr;



	dir = pgd_offset_k(addr);

	p4dp = p4d_offset(dir, addr);

	pudp = pud_offset(p4dp, addr);

	pmdp = pmd_offset(pudp, addr);

	ptep = pte_offset_kernel(pmdp, addr);

	*ptep = pte_mknocache(*ptep);

}



/*

 * Enable caching for page at given kernel virtual address.

 */

static inline void cache_page(void *vaddr)

{

	pgd_t *dir;

	p4d_t *p4dp;

	pud_t *pudp;

	pmd_t *pmdp;

	pte_t *ptep;

	unsigned long addr = (unsigned long) vaddr;



	dir = pgd_offset_k(addr);

	p4dp = p4d_offset(dir, addr);

	pudp = pud_offset(p4dp, addr);

	pmdp = pmd_offset(pudp, addr);

	ptep = pte_offset_kernel(pmdp, addr);

	*ptep = pte_mkcache(*ptep);

}



/*

 * Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e))

 */

arch/m68k/include/asm/motorola_pgtable.h

+0 −44
Original line number Diff line number Diff line
@@ -227,50 +227,6 @@ static inline pte_t *pte_offset_kernel(pmd_t *pmdp, unsigned long address) 
#define pte_offset_map(pmdp,address) ((pte_t *)__pmd_page(*pmdp) + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))

#define pte_unmap(pte)		((void)0)



/* Prior to calling these routines, the page should have been flushed

 * from both the cache and ATC, or the CPU might not notice that the

 * cache setting for the page has been changed. -jskov

 */

static inline void nocache_page(void *vaddr)

{

	unsigned long addr = (unsigned long)vaddr;



	if (CPU_IS_040_OR_060) {

		pgd_t *dir;

		p4d_t *p4dp;

		pud_t *pudp;

		pmd_t *pmdp;

		pte_t *ptep;



		dir = pgd_offset_k(addr);

		p4dp = p4d_offset(dir, addr);

		pudp = pud_offset(p4dp, addr);

		pmdp = pmd_offset(pudp, addr);

		ptep = pte_offset_kernel(pmdp, addr);

		*ptep = pte_mknocache(*ptep);

	}

}



static inline void cache_page(void *vaddr)

{

	unsigned long addr = (unsigned long)vaddr;



	if (CPU_IS_040_OR_060) {

		pgd_t *dir;

		p4d_t *p4dp;

		pud_t *pudp;

		pmd_t *pmdp;

		pte_t *ptep;



		dir = pgd_offset_k(addr);

		p4dp = p4d_offset(dir, addr);

		pudp = pud_offset(p4dp, addr);

		pmdp = pmd_offset(pudp, addr);

		ptep = pte_offset_kernel(pmdp, addr);

		*ptep = pte_mkcache(*ptep);

	}

}



/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */

#define __swp_type(x)		(((x).val >> 4) & 0xff)

#define __swp_offset(x)		((x).val >> 12)

arch/m68k/mm/motorola.c

+43 −0
Original line number Diff line number Diff line
@@ -45,6 +45,49 @@ unsigned long mm_cachebits; 
EXPORT_SYMBOL(mm_cachebits);

#endif



/* Prior to calling these routines, the page should have been flushed

 * from both the cache and ATC, or the CPU might not notice that the

 * cache setting for the page has been changed. -jskov

 */

static inline void nocache_page(void *vaddr)

{

	unsigned long addr = (unsigned long)vaddr;



	if (CPU_IS_040_OR_060) {

		pgd_t *dir;

		p4d_t *p4dp;

		pud_t *pudp;

		pmd_t *pmdp;

		pte_t *ptep;



		dir = pgd_offset_k(addr);

		p4dp = p4d_offset(dir, addr);

		pudp = pud_offset(p4dp, addr);

		pmdp = pmd_offset(pudp, addr);

		ptep = pte_offset_kernel(pmdp, addr);

		*ptep = pte_mknocache(*ptep);

	}

}



static inline void cache_page(void *vaddr)

{

	unsigned long addr = (unsigned long)vaddr;



	if (CPU_IS_040_OR_060) {

		pgd_t *dir;

		p4d_t *p4dp;

		pud_t *pudp;

		pmd_t *pmdp;

		pte_t *ptep;



		dir = pgd_offset_k(addr);

		p4dp = p4d_offset(dir, addr);

		pudp = pud_offset(p4dp, addr);

		pmdp = pmd_offset(pudp, addr);

		ptep = pte_offset_kernel(pmdp, addr);

		*ptep = pte_mkcache(*ptep);

	}

}



/*

 * Motorola 680x0 user's manual recommends using uncached memory for address

CRA Git | Maintained and supported by SUSTech CRA and CCSE