Commit 1bab09ac authored by Lyude Paul's avatar Lyude Paul Committed by Ben Skeggs
Browse files

drm/nouveau: Add support for BLCG on Kepler1 



This enables BLCG optimization for kepler1. When using clockgating,
nvidia's firmware has a set of registers which are initially programmed
by the vbios with various engine delays and other mysterious settings
that are safe enough to bring up the GPU. However, the values used by
the vbios are more power hungry then they need to be, so the nvidia driver
writes it's own more optimized set of BLCG settings before enabling
CG_CTRL. This adds support for programming the optimized BLCG values
during engine/subdev init, which enables rather significant power
savings.

This introduces the nvkm_therm_clkgate_init() helper, which we use to
program the optimized BLCG settings before enabling clockgating with
nvkm_therm_clkgate_enable.

As well, this commit shares a lot more code with Fermi since BLCG is
mostly the same there as far as we can tell. In the future, it's likely
we'll reformat the clkgate_packs for kepler1 so that they share a list
of mmio packs with Fermi.

Signed-off-by: default avatarLyude Paul <lyude@redhat.com>
Reviewed-by: default avatarMartin Peres <martin.peres@free.fr>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent b138eca6

drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h

+12 −0
Original line number Diff line number Diff line
@@ -46,6 +46,16 @@ enum nvkm_therm_attr_type { 
	NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST = 17,

};



struct nvkm_therm_clkgate_init {

	u32 addr;

	u8  count;

	u32 data;

};



struct nvkm_therm_clkgate_pack {

	const struct nvkm_therm_clkgate_init *init;

};



struct nvkm_therm {

	const struct nvkm_therm_func *func;

	struct nvkm_subdev subdev;
@@ -92,6 +102,8 @@ struct nvkm_therm { 
int nvkm_therm_temp_get(struct nvkm_therm *);

int nvkm_therm_fan_sense(struct nvkm_therm *);

int nvkm_therm_cstate(struct nvkm_therm *, int, int);

void nvkm_therm_clkgate_init(struct nvkm_therm *,

			     const struct nvkm_therm_clkgate_pack *);

void nvkm_therm_clkgate_enable(struct nvkm_therm *);

void nvkm_therm_clkgate_fini(struct nvkm_therm *, bool);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

+1 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ struct gf100_gr_func { 
	int (*rops)(struct gf100_gr *);

	int ppc_nr;

	const struct gf100_grctx_func *grctx;

	const struct nvkm_therm_clkgate_pack *clkgate_pack;

	struct nvkm_sclass sclass[];

};

drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c

+207 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
 * Authors: Ben Skeggs <bskeggs@redhat.com>

 */

#include "gf100.h"

#include "gk104.h"

#include "ctxgf100.h"



#include <nvif/class.h>
@@ -173,6 +174,208 @@ gk104_gr_pack_mmio[] = { 
	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_main_0[] = {

	{ 0x4041f0, 1, 0x00004046 },

	{ 0x409890, 1, 0x00000045 },

	{ 0x4098b0, 1, 0x0000007f },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_rstr2d_0[] = {

	{ 0x4078c0, 1, 0x00000042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_unk_0[] = {

	{ 0x406000, 1, 0x00004044 },

	{ 0x405860, 1, 0x00004042 },

	{ 0x40590c, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gcc_0[] = {

	{ 0x408040, 1, 0x00004044 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_sked_0[] = {

	{ 0x407000, 1, 0x00004044 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_unk_1[] = {

	{ 0x405bf0, 1, 0x00004044 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_ctxctl_0[] = {

	{ 0x41a890, 1, 0x00000042 },

	{ 0x41a8b0, 1, 0x0000007f },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_unk_0[] = {

	{ 0x418500, 1, 0x00004042 },

	{ 0x418608, 1, 0x00004042 },

	{ 0x418688, 1, 0x00004042 },

	{ 0x418718, 1, 0x00000042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_esetup_0[] = {

	{ 0x418828, 1, 0x00000044 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_tpbus_0[] = {

	{ 0x418bbc, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_zcull_0[] = {

	{ 0x418970, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_tpconf_0[] = {

	{ 0x418c70, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_unk_1[] = {

	{ 0x418cf0, 1, 0x00004042 },

	{ 0x418d70, 1, 0x00004042 },

	{ 0x418f0c, 1, 0x00004042 },

	{ 0x418e0c, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_gcc_0[] = {

	{ 0x419020, 1, 0x00004042 },

	{ 0x419038, 1, 0x00000042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_ffb_0[] = {

	{ 0x418898, 1, 0x00000042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_tex_0[] = {

	{ 0x419a40, 9, 0x00004042 },

	{ 0x419acc, 1, 0x00004047 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_poly_0[] = {

	{ 0x419868, 1, 0x00000042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_l1c_0[] = {

	{ 0x419ccc, 3, 0x00000042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_unk_2[] = {

	{ 0x419c70, 1, 0x00004045 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_mp_0[] = {

	{ 0x419fd0, 1, 0x00004043 },

	{ 0x419fd8, 1, 0x00004049 },

	{ 0x419fe0, 2, 0x00004042 },

	{ 0x419ff0, 1, 0x00004046 },

	{ 0x419ff8, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_gpc_ppc_0[] = {

	{ 0x41be28, 1, 0x00000042 },

	{ 0x41bfe8, 1, 0x00004042 },

	{ 0x41bed0, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_rop_zrop_0[] = {

	{ 0x408810, 2, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_rop_0[] = {

	{ 0x408a80, 6, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_rop_crop_0[] = {

	{ 0x4089a8, 1, 0x00004042 },

	{ 0x4089b0, 1, 0x00000042 },

	{ 0x4089b8, 1, 0x00004042 },

	{}

};



const struct nvkm_therm_clkgate_init

gk104_clkgate_blcg_init_pxbar_0[] = {

	{ 0x13c820, 1, 0x0001007f },

	{ 0x13cbe0, 1, 0x00000042 },

	{}

};



static const struct nvkm_therm_clkgate_pack

gk104_clkgate_pack[] = {

	{ gk104_clkgate_blcg_init_main_0 },

	{ gk104_clkgate_blcg_init_rstr2d_0 },

	{ gk104_clkgate_blcg_init_unk_0 },

	{ gk104_clkgate_blcg_init_gcc_0 },

	{ gk104_clkgate_blcg_init_sked_0 },

	{ gk104_clkgate_blcg_init_unk_1 },

	{ gk104_clkgate_blcg_init_gpc_ctxctl_0 },

	{ gk104_clkgate_blcg_init_gpc_unk_0 },

	{ gk104_clkgate_blcg_init_gpc_esetup_0 },

	{ gk104_clkgate_blcg_init_gpc_tpbus_0 },

	{ gk104_clkgate_blcg_init_gpc_zcull_0 },

	{ gk104_clkgate_blcg_init_gpc_tpconf_0 },

	{ gk104_clkgate_blcg_init_gpc_unk_1 },

	{ gk104_clkgate_blcg_init_gpc_gcc_0 },

	{ gk104_clkgate_blcg_init_gpc_ffb_0 },

	{ gk104_clkgate_blcg_init_gpc_tex_0 },

	{ gk104_clkgate_blcg_init_gpc_poly_0 },

	{ gk104_clkgate_blcg_init_gpc_l1c_0 },

	{ gk104_clkgate_blcg_init_gpc_unk_2 },

	{ gk104_clkgate_blcg_init_gpc_mp_0 },

	{ gk104_clkgate_blcg_init_gpc_ppc_0 },

	{ gk104_clkgate_blcg_init_rop_zrop_0 },

	{ gk104_clkgate_blcg_init_rop_0 },

	{ gk104_clkgate_blcg_init_rop_crop_0 },

	{ gk104_clkgate_blcg_init_pxbar_0 },

	{}

};



/*******************************************************************************

 * PGRAPH engine/subdev functions

 ******************************************************************************/
@@ -214,6 +417,9 @@ gk104_gr_init(struct gf100_gr *gr) 
	gr->func->init_gpc_mmu(gr);



	gf100_gr_mmio(gr, gr->func->mmio);

	if (gr->func->clkgate_pack)

		nvkm_therm_clkgate_init(gr->base.engine.subdev.device->therm,

					gr->func->clkgate_pack);



	nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
@@ -338,6 +544,7 @@ gk104_gr = { 
	.rops = gf100_gr_rops,

	.ppc_nr = 1,

	.grctx = &gk104_grctx,

	.clkgate_pack = gk104_clkgate_pack,

	.sclass = {

		{ -1, -1, FERMI_TWOD_A },

		{ -1, -1, KEPLER_INLINE_TO_MEMORY_A },

drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.h

0 → 100644
+55 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Lyude Paul <lyude@redhat.com>

 */

#ifndef __GK104_GR_H__

#define __GK104_GR_H__



#include <subdev/therm.h>



extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_main_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_rstr2d_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_unk_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gcc_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_sked_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_unk_1[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_ctxctl_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_unk_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_esetup_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_tpbus_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_zcull_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_tpconf_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_unk_1[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_gcc_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_ffb_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_tex_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_poly_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_l1c_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_unk_2[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_mp_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_gpc_ppc_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_rop_zrop_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_rop_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_rop_crop_0[];

extern const struct nvkm_therm_clkgate_init gk104_clkgate_blcg_init_pxbar_0[];



#endif

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c

+6 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 


#include <core/memory.h>

#include <core/option.h>

#include <subdev/therm.h>



void

gf100_fb_intr(struct nvkm_fb *base)
@@ -92,6 +93,11 @@ gf100_fb_init(struct nvkm_fb *base) 


	if (fb->r100c10_page)

		nvkm_wr32(device, 0x100c10, fb->r100c10 >> 8);



	if (base->func->clkgate_pack) {

		nvkm_therm_clkgate_init(device->therm,

					base->func->clkgate_pack);

	}

}



void *

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