Commit 1b77be46 authored by Vinay Kumar Yadav's avatar Vinay Kumar Yadav Committed by David S. Miller
Browse files

crypto/chcr: Moving chelsio's inline ipsec functionality to /drivers/net



This patch seperates inline ipsec functionality from coprocessor
driver chcr. Now inline ipsec is separate ULD, moved from
"drivers/crypto/chelsio/" to "drivers/net/ethernet/chelsio/inline_crypto/ch_ipsec/"

Signed-off-by: default avatarAyush Sawal <ayush.sawal@chelsio.com>
Signed-off-by: default avatarVinay Kumar Yadav <vinay.yadav@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 44fd1c1f
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+0 −10
Original line number Diff line number Diff line
@@ -22,16 +22,6 @@ config CRYPTO_DEV_CHELSIO
	  To compile this driver as a module, choose M here: the module
	  will be called chcr.

config CHELSIO_IPSEC_INLINE
	bool "Chelsio IPSec XFRM Tx crypto offload"
	depends on CHELSIO_T4
	depends on CRYPTO_DEV_CHELSIO
	depends on XFRM_OFFLOAD
	depends on INET_ESP_OFFLOAD || INET6_ESP_OFFLOAD
	default n
	help
	  Enable support for IPSec Tx Inline.

config CHELSIO_TLS_DEVICE
	bool "Chelsio Inline KTLS Offload"
	depends on CHELSIO_T4
+0 −1
Original line number Diff line number Diff line
@@ -6,4 +6,3 @@ chcr-objs := chcr_core.o chcr_algo.o
#ifdef CONFIG_CHELSIO_TLS_DEVICE
chcr-objs += chcr_ktls.o
#endif
chcr-$(CONFIG_CHELSIO_IPSEC_INLINE) += chcr_ipsec.o
+2 −40
Original line number Diff line number Diff line
@@ -40,10 +40,6 @@ static const struct tlsdev_ops chcr_ktls_ops = {
};
#endif

#ifdef CONFIG_CHELSIO_IPSEC_INLINE
static void update_netdev_features(void);
#endif /* CONFIG_CHELSIO_IPSEC_INLINE */

static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {
	[CPL_FW6_PLD] = cpl_fw6_pld_handler,
#ifdef CONFIG_CHELSIO_TLS_DEVICE
@@ -60,10 +56,8 @@ static struct cxgb4_uld_info chcr_uld_info = {
	.add = chcr_uld_add,
	.state_change = chcr_uld_state_change,
	.rx_handler = chcr_uld_rx_handler,
#if defined(CONFIG_CHELSIO_IPSEC_INLINE) || defined(CONFIG_CHELSIO_TLS_DEVICE)
	.tx_handler = chcr_uld_tx_handler,
#endif /* CONFIG_CHELSIO_IPSEC_INLINE || CONFIG_CHELSIO_TLS_DEVICE */
#if defined(CONFIG_CHELSIO_TLS_DEVICE)
	.tx_handler = chcr_uld_tx_handler,
	.tlsdev_ops = &chcr_ktls_ops,
#endif
};
@@ -241,19 +235,11 @@ int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
	return 0;
}

#if defined(CONFIG_CHELSIO_IPSEC_INLINE) || defined(CONFIG_CHELSIO_TLS_DEVICE)
#if defined(CONFIG_CHELSIO_TLS_DEVICE)
int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev)
{
	/* In case if skb's decrypted bit is set, it's nic tls packet, else it's
	 * ipsec packet.
	 */
#ifdef CONFIG_CHELSIO_TLS_DEVICE
	if (skb->decrypted)
		return chcr_ktls_xmit(skb, dev);
#endif
#ifdef CONFIG_CHELSIO_IPSEC_INLINE
	return chcr_ipsec_xmit(skb, dev);
#endif
	return 0;
}
#endif /* CONFIG_CHELSIO_IPSEC_INLINE || CONFIG_CHELSIO_TLS_DEVICE */
@@ -305,24 +291,6 @@ static int chcr_uld_state_change(void *handle, enum cxgb4_state state)
	return ret;
}

#ifdef CONFIG_CHELSIO_IPSEC_INLINE
static void update_netdev_features(void)
{
	struct uld_ctx *u_ctx, *tmp;

	mutex_lock(&drv_data.drv_mutex);
	list_for_each_entry_safe(u_ctx, tmp, &drv_data.inact_dev, entry) {
		if (u_ctx->lldi.crypto & ULP_CRYPTO_IPSEC_INLINE)
			chcr_add_xfrmops(&u_ctx->lldi);
	}
	list_for_each_entry_safe(u_ctx, tmp, &drv_data.act_dev, entry) {
		if (u_ctx->lldi.crypto & ULP_CRYPTO_IPSEC_INLINE)
			chcr_add_xfrmops(&u_ctx->lldi);
	}
	mutex_unlock(&drv_data.drv_mutex);
}
#endif /* CONFIG_CHELSIO_IPSEC_INLINE */

static int __init chcr_crypto_init(void)
{
	INIT_LIST_HEAD(&drv_data.act_dev);
@@ -332,12 +300,6 @@ static int __init chcr_crypto_init(void)
	drv_data.last_dev = NULL;
	cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info);

	#ifdef CONFIG_CHELSIO_IPSEC_INLINE
	rtnl_lock();
	update_netdev_features();
	rtnl_unlock();
	#endif /* CONFIG_CHELSIO_IPSEC_INLINE */

	return 0;
}

+0 −31
Original line number Diff line number Diff line
@@ -109,37 +109,6 @@ struct uld_ctx {
	struct chcr_dev dev;
};

struct chcr_ipsec_req {
	struct ulp_txpkt ulptx;
	struct ulptx_idata sc_imm;
	struct cpl_tx_sec_pdu sec_cpl;
	struct _key_ctx key_ctx;
};

struct chcr_ipsec_wr {
	struct fw_ulptx_wr wreq;
	struct chcr_ipsec_req req;
};

#define ESN_IV_INSERT_OFFSET 12
struct chcr_ipsec_aadiv {
	__be32 spi;
	u8 seq_no[8];
	u8 iv[8];
};

struct ipsec_sa_entry {
	int hmac_ctrl;
	u16 esn;
	u16 resv;
	unsigned int enckey_len;
	unsigned int kctx_len;
	unsigned int authsize;
	__be32 key_ctx_hdr;
	char salt[MAX_SALT];
	char key[2 * AES_MAX_KEY_SIZE];
};

/*
 *      sgl_len - calculates the size of an SGL of the given capacity
 *      @n: the number of SGL entries
+3 −0
Original line number Diff line number Diff line
@@ -1196,6 +1196,9 @@ struct adapter {
	struct cxgb4_tc_u32_table *tc_u32;
	struct chcr_ktls chcr_ktls;
	struct chcr_stats_debug chcr_stats;
#if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE)
	struct ch_ipsec_stats_debug ch_ipsec_stats;
#endif

	/* TC flower offload */
	bool tc_flower_initialized;
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