Commit 1b39d5f2 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

gpio/samsung: gpio-samsung.c to support Samsung GPIOs 



This patch adds support for Samsung GPIOs with one gpio driver
and removes old GPIO drivers which are drivers/gpio-s3c24xx.c,
gpio-s3c64xx.c, gpio-s5p64x0.c, gpio-s5pc100.c, gpio-s5pv210.c,
gpio-exynos4.c, gpio-plat-samsung.c, plat-samsung/gpio-config.c
and gpio.c to support each Samsung SoCs before. Because the
gpio-samsung.c can replace old Samsung GPIO drivers.
Basically, the gpio-samsung.c has been made by their merging
and removing duplicated definitions.

Note: gpio-samsung.c includes some SoC dependent codes and it
will be replaced next time.

Cc: Ben Dooks <ben-linux@fluff.org>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
[kgene.kim@samsung.com: squash the removing and adding patches]
[kgene.kim@samsung.com: fixes bug during to register of gpio_chips]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent c4b3fd38

arch/arm/plat-samsung/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -15,8 +15,6 @@ obj-y += init.o 
obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o

obj-y				+= clock.o

obj-y				+= pwm-clock.o

obj-y				+= gpio.o

obj-y				+= gpio-config.o

obj-y				+= dev-asocdma.o



obj-$(CONFIG_SAMSUNG_CLKSRC)	+= clock-clksrc.o

arch/arm/plat-samsung/gpio-config.c

deleted100644 → 0
+0 −431
Original line number Diff line number Diff line 
/* linux/arch/arm/plat-s3c/gpio-config.c

 *

 * Copyright 2008 Openmoko, Inc.

 * Copyright 2008-2010 Simtec Electronics

 *	Ben Dooks <ben@simtec.co.uk>

 *	http://armlinux.simtec.co.uk/

 *

 * S3C series GPIO configuration core

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/gpio.h>

#include <linux/io.h>



#include <plat/gpio-core.h>

#include <plat/gpio-cfg.h>

#include <plat/gpio-cfg-helpers.h>



int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)

{

	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);

	unsigned long flags;

	int offset;

	int ret;



	if (!chip)

		return -EINVAL;



	offset = pin - chip->chip.base;



	s3c_gpio_lock(chip, flags);

	ret = s3c_gpio_do_setcfg(chip, offset, config);

	s3c_gpio_unlock(chip, flags);



	return ret;

}

EXPORT_SYMBOL(s3c_gpio_cfgpin);



int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,

			  unsigned int cfg)

{

	int ret;



	for (; nr > 0; nr--, start++) {

		ret = s3c_gpio_cfgpin(start, cfg);

		if (ret != 0)

			return ret;

	}



	return 0;

}

EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);



int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,

			  unsigned int cfg, s3c_gpio_pull_t pull)

{

	int ret;



	for (; nr > 0; nr--, start++) {

		s3c_gpio_setpull(start, pull);

		ret = s3c_gpio_cfgpin(start, cfg);

		if (ret != 0)

			return ret;

	}



	return 0;

}

EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);



unsigned s3c_gpio_getcfg(unsigned int pin)

{

	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);

	unsigned long flags;

	unsigned ret = 0;

	int offset;



	if (chip) {

		offset = pin - chip->chip.base;



		s3c_gpio_lock(chip, flags);

		ret = s3c_gpio_do_getcfg(chip, offset);

		s3c_gpio_unlock(chip, flags);

	}



	return ret;

}

EXPORT_SYMBOL(s3c_gpio_getcfg);





int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)

{

	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);

	unsigned long flags;

	int offset, ret;



	if (!chip)

		return -EINVAL;



	offset = pin - chip->chip.base;



	s3c_gpio_lock(chip, flags);

	ret = s3c_gpio_do_setpull(chip, offset, pull);

	s3c_gpio_unlock(chip, flags);



	return ret;

}

EXPORT_SYMBOL(s3c_gpio_setpull);



s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin)

{

	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);

	unsigned long flags;

	int offset;

	u32 pup = 0;



	if (chip) {

		offset = pin - chip->chip.base;



		s3c_gpio_lock(chip, flags);

		pup = s3c_gpio_do_getpull(chip, offset);

		s3c_gpio_unlock(chip, flags);

	}



	return (__force s3c_gpio_pull_t)pup;

}

EXPORT_SYMBOL(s3c_gpio_getpull);



#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX

int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,

			      unsigned int off, unsigned int cfg)

{

	void __iomem *reg = chip->base;

	unsigned int shift = off;

	u32 con;



	if (s3c_gpio_is_cfg_special(cfg)) {

		cfg &= 0xf;



		/* Map output to 0, and SFN2 to 1 */

		cfg -= 1;

		if (cfg > 1)

			return -EINVAL;



		cfg <<= shift;

	}



	con = __raw_readl(reg);

	con &= ~(0x1 << shift);

	con |= cfg;

	__raw_writel(con, reg);



	return 0;

}



unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,

				   unsigned int off)

{

	u32 con;



	con = __raw_readl(chip->base);

	con >>= off;

	con &= 1;

	con++;



	return S3C_GPIO_SFN(con);

}



int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,

			    unsigned int off, unsigned int cfg)

{

	void __iomem *reg = chip->base;

	unsigned int shift = off * 2;

	u32 con;



	if (s3c_gpio_is_cfg_special(cfg)) {

		cfg &= 0xf;

		if (cfg > 3)

			return -EINVAL;



		cfg <<= shift;

	}



	con = __raw_readl(reg);

	con &= ~(0x3 << shift);

	con |= cfg;

	__raw_writel(con, reg);



	return 0;

}



unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,

				     unsigned int off)

{

	u32 con;



	con = __raw_readl(chip->base);

	con >>= off * 2;

	con &= 3;



	/* this conversion works for IN and OUT as well as special mode */

	return S3C_GPIO_SPECIAL(con);

}

#endif



#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX

int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,

				 unsigned int off, unsigned int cfg)

{

	void __iomem *reg = chip->base;

	unsigned int shift = (off & 7) * 4;

	u32 con;



	if (off < 8 && chip->chip.ngpio > 8)

		reg -= 4;



	if (s3c_gpio_is_cfg_special(cfg)) {

		cfg &= 0xf;

		cfg <<= shift;

	}



	con = __raw_readl(reg);

	con &= ~(0xf << shift);

	con |= cfg;

	__raw_writel(con, reg);



	return 0;

}



unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,

				      unsigned int off)

{

	void __iomem *reg = chip->base;

	unsigned int shift = (off & 7) * 4;

	u32 con;



	if (off < 8 && chip->chip.ngpio > 8)

		reg -= 4;



	con = __raw_readl(reg);

	con >>= shift;

	con &= 0xf;



	/* this conversion works for IN and OUT as well as special mode */

	return S3C_GPIO_SPECIAL(con);

}



#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */



#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN

int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,

			    unsigned int off, s3c_gpio_pull_t pull)

{

	void __iomem *reg = chip->base + 0x08;

	int shift = off * 2;

	u32 pup;



	pup = __raw_readl(reg);

	pup &= ~(3 << shift);

	pup |= pull << shift;

	__raw_writel(pup, reg);



	return 0;

}



s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,

					unsigned int off)

{

	void __iomem *reg = chip->base + 0x08;

	int shift = off * 2;

	u32 pup = __raw_readl(reg);



	pup >>= shift;

	pup &= 0x3;

	return (__force s3c_gpio_pull_t)pup;

}



#ifdef CONFIG_S3C_GPIO_PULL_S3C2443

int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,

				unsigned int off, s3c_gpio_pull_t pull)

{

	switch (pull) {

	case S3C_GPIO_PULL_NONE:

		pull = 0x01;

		break;

	case S3C_GPIO_PULL_UP:

		pull = 0x00;

		break;

	case S3C_GPIO_PULL_DOWN:

		pull = 0x02;

		break;

	}

	return s3c_gpio_setpull_updown(chip, off, pull);

}



s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip,

					unsigned int off)

{

	s3c_gpio_pull_t pull;



	pull = s3c_gpio_getpull_updown(chip, off);



	switch (pull) {

	case 0x00:

		pull = S3C_GPIO_PULL_UP;

		break;

	case 0x01:

	case 0x03:

		pull = S3C_GPIO_PULL_NONE;

		break;

	case 0x02:

		pull = S3C_GPIO_PULL_DOWN;

		break;

	}



	return pull;

}

#endif

#endif



#if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN)

static int s3c_gpio_setpull_1(struct s3c_gpio_chip *chip,

			 unsigned int off, s3c_gpio_pull_t pull,

			 s3c_gpio_pull_t updown)

{

	void __iomem *reg = chip->base + 0x08;

	u32 pup = __raw_readl(reg);



	if (pull == updown)

		pup &= ~(1 << off);

	else if (pull == S3C_GPIO_PULL_NONE)

		pup |= (1 << off);

	else

		return -EINVAL;



	__raw_writel(pup, reg);

	return 0;

}



static s3c_gpio_pull_t s3c_gpio_getpull_1(struct s3c_gpio_chip *chip,

				     unsigned int off, s3c_gpio_pull_t updown)

{

	void __iomem *reg = chip->base + 0x08;

	u32 pup = __raw_readl(reg);



	pup &= (1 << off);

	return pup ? S3C_GPIO_PULL_NONE : updown;

}

#endif /* CONFIG_S3C_GPIO_PULL_UP || CONFIG_S3C_GPIO_PULL_DOWN */



#ifdef CONFIG_S3C_GPIO_PULL_UP

s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,

				     unsigned int off)

{

	return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);

}



int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,

			 unsigned int off, s3c_gpio_pull_t pull)

{

	return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);

}

#endif /* CONFIG_S3C_GPIO_PULL_UP */



#ifdef CONFIG_S3C_GPIO_PULL_DOWN

s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,

				     unsigned int off)

{

	return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);

}



int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,

			 unsigned int off, s3c_gpio_pull_t pull)

{

	return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);

}

#endif /* CONFIG_S3C_GPIO_PULL_DOWN */



#ifdef CONFIG_S5P_GPIO_DRVSTR

s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)

{

	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);

	unsigned int off;

	void __iomem *reg;

	int shift;

	u32 drvstr;



	if (!chip)

		return -EINVAL;



	off = pin - chip->chip.base;

	shift = off * 2;

	reg = chip->base + 0x0C;



	drvstr = __raw_readl(reg);

	drvstr = drvstr >> shift;

	drvstr &= 0x3;



	return (__force s5p_gpio_drvstr_t)drvstr;

}

EXPORT_SYMBOL(s5p_gpio_get_drvstr);



int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)

{

	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);

	unsigned int off;

	void __iomem *reg;

	int shift;

	u32 tmp;



	if (!chip)

		return -EINVAL;



	off = pin - chip->chip.base;

	shift = off * 2;

	reg = chip->base + 0x0C;



	tmp = __raw_readl(reg);

	tmp &= ~(0x3 << shift);

	tmp |= drvstr << shift;



	__raw_writel(tmp, reg);



	return 0;

}

EXPORT_SYMBOL(s5p_gpio_set_drvstr);

#endif	/* CONFIG_S5P_GPIO_DRVSTR */

arch/arm/plat-samsung/gpio.c

deleted100644 → 0
+0 −167
Original line number Diff line number Diff line 
/* linux/arch/arm/plat-s3c/gpio.c

 *

 * Copyright 2008 Simtec Electronics

 *	Ben Dooks <ben@simtec.co.uk>

 *	http://armlinux.simtec.co.uk/

 *

 * S3C series GPIO core

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/gpio.h>

#include <linux/spinlock.h>



#include <plat/gpio-core.h>



#ifdef CONFIG_S3C_GPIO_TRACK

struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];



static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)

{

	unsigned int gpn;

	int i;



	gpn = chip->chip.base;

	for (i = 0; i < chip->chip.ngpio; i++, gpn++) {

		BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));

		s3c_gpios[gpn] = chip;

	}

}

#endif /* CONFIG_S3C_GPIO_TRACK */



/* Default routines for controlling GPIO, based on the original S3C24XX

 * GPIO functions which deal with the case where each gpio bank of the

 * chip is as following:

 *

 * base + 0x00: Control register, 2 bits per gpio

 *	        gpio n: 2 bits starting at (2*n)

 *		00 = input, 01 = output, others mean special-function

 * base + 0x04: Data register, 1 bit per gpio

 *		bit n: data bit n

*/



static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)

{

	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);

	void __iomem *base = ourchip->base;

	unsigned long flags;

	unsigned long con;



	s3c_gpio_lock(ourchip, flags);



	con = __raw_readl(base + 0x00);

	con &= ~(3 << (offset * 2));



	__raw_writel(con, base + 0x00);



	s3c_gpio_unlock(ourchip, flags);

	return 0;

}



static int s3c_gpiolib_output(struct gpio_chip *chip,

			      unsigned offset, int value)

{

	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);

	void __iomem *base = ourchip->base;

	unsigned long flags;

	unsigned long dat;

	unsigned long con;



	s3c_gpio_lock(ourchip, flags);



	dat = __raw_readl(base + 0x04);

	dat &= ~(1 << offset);

	if (value)

		dat |= 1 << offset;

	__raw_writel(dat, base + 0x04);



	con = __raw_readl(base + 0x00);

	con &= ~(3 << (offset * 2));

	con |= 1 << (offset * 2);



	__raw_writel(con, base + 0x00);

	__raw_writel(dat, base + 0x04);



	s3c_gpio_unlock(ourchip, flags);

	return 0;

}



static void s3c_gpiolib_set(struct gpio_chip *chip,

			    unsigned offset, int value)

{

	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);

	void __iomem *base = ourchip->base;

	unsigned long flags;

	unsigned long dat;



	s3c_gpio_lock(ourchip, flags);



	dat = __raw_readl(base + 0x04);

	dat &= ~(1 << offset);

	if (value)

		dat |= 1 << offset;

	__raw_writel(dat, base + 0x04);



	s3c_gpio_unlock(ourchip, flags);

}



static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)

{

	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);

	unsigned long val;



	val = __raw_readl(ourchip->base + 0x04);

	val >>= offset;

	val &= 1;



	return val;

}



__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)

{

	struct gpio_chip *gc = &chip->chip;

	int ret;



	BUG_ON(!chip->base);

	BUG_ON(!gc->label);

	BUG_ON(!gc->ngpio);



	spin_lock_init(&chip->lock);



	if (!gc->direction_input)

		gc->direction_input = s3c_gpiolib_input;

	if (!gc->direction_output)

		gc->direction_output = s3c_gpiolib_output;

	if (!gc->set)

		gc->set = s3c_gpiolib_set;

	if (!gc->get)

		gc->get = s3c_gpiolib_get;



#ifdef CONFIG_PM

	if (chip->pm != NULL) {

		if (!chip->pm->save || !chip->pm->resume)

			printk(KERN_ERR "gpio: %s has missing PM functions\n",

			       gc->label);

	} else

		printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);

#endif



	/* gpiochip_add() prints own failure message on error. */

	ret = gpiochip_add(gc);

	if (ret >= 0)

		s3c_gpiolib_track(chip);

}



int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)

{

	struct s3c_gpio_chip *s3c_chip = container_of(chip,

			struct s3c_gpio_chip, chip);



	return s3c_chip->irq_base + offset;

}

drivers/gpio/Kconfig

+0 −28
Original line number Diff line number Diff line
@@ -95,10 +95,6 @@ config GPIO_EP93XX 
	depends on ARCH_EP93XX

	select GPIO_GENERIC



config GPIO_EXYNOS4

	def_bool y

	depends on CPU_EXYNOS4210



config GPIO_MPC5200

	def_bool y

	depends on PPC_MPC52xx
@@ -131,30 +127,6 @@ config GPIO_MXS 
	select GPIO_GENERIC

	select GENERIC_IRQ_CHIP



config GPIO_PLAT_SAMSUNG

	def_bool y

	depends on SAMSUNG_GPIOLIB_4BIT



config GPIO_S3C24XX

	def_bool y

	depends on PLAT_S3C24XX



config GPIO_S3C64XX

	def_bool y

	depends on ARCH_S3C64XX



config GPIO_S5P64X0

	def_bool y

	depends on ARCH_S5P64X0



config GPIO_S5PC100

	def_bool y

	depends on CPU_S5PC100



config GPIO_S5PV210

	def_bool y

	depends on CPU_S5PV210



config GPIO_PL061

	bool "PrimeCell PL061 GPIO support"

	depends on ARM_AMBA

drivers/gpio/Makefile

+1 −9
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o 
obj-$(CONFIG_GPIO_CS5535)	+= gpio-cs5535.o

obj-$(CONFIG_GPIO_DA9052)	+= gpio-da9052.o

obj-$(CONFIG_GPIO_EP93XX)	+= gpio-ep93xx.o

obj-$(CONFIG_GPIO_EXYNOS4)	+= gpio-exynos4.o

obj-$(CONFIG_GPIO_IT8761E)	+= gpio-it8761e.o

obj-$(CONFIG_GPIO_JANZ_TTL)	+= gpio-janz-ttl.o

obj-$(CONFIG_GPIO_LANGWELL)	+= gpio-langwell.o
@@ -38,14 +37,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o 
obj-$(CONFIG_GPIO_PCH)		+= gpio-pch.o

obj-$(CONFIG_GPIO_PL061)	+= gpio-pl061.o

obj-$(CONFIG_GPIO_RDC321X)	+= gpio-rdc321x.o



obj-$(CONFIG_GPIO_PLAT_SAMSUNG)	+= gpio-plat-samsung.o

obj-$(CONFIG_GPIO_S3C24XX)	+= gpio-s3c24xx.o

obj-$(CONFIG_GPIO_S3C64XX)	+= gpio-s3c64xx.o

obj-$(CONFIG_GPIO_S5P64X0)	+= gpio-s5p64x0.o

obj-$(CONFIG_GPIO_S5PC100)	+= gpio-s5pc100.o

obj-$(CONFIG_GPIO_S5PV210)	+= gpio-s5pv210.o



obj-$(CONFIG_PLAT_SAMSUNG)	+= gpio-samsung.o

obj-$(CONFIG_GPIO_SCH)		+= gpio-sch.o

obj-$(CONFIG_GPIO_STMPE)	+= gpio-stmpe.o

obj-$(CONFIG_GPIO_SX150X)	+= gpio-sx150x.o

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