Commit 1b37b8c4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp 

Pull EDAC updates from Borislav Petkov:

 - A new EDAC AST 2500 SoC driver (Stefan M Schaeckeler)

 - New i10nm EDAC driver for Intel 10nm CPUs (Qiuxu Zhuo and Tony Luck)

 - Altera SDRAM functionality carveout for separate enablement of RAS
   and SDRAM capabilities on some Altera chips. (Thor Thayer)

 - The usual round of cleanups and fixes

And last but not least: recruit James Morse as a reviewer for the ARM
side.

* tag 'edac_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  EDAC/altera: Add separate SDRAM EDAC config
  EDAC, altera: Add missing of_node_put()
  EDAC, skx_common: Add code to recognise new compound error code
  EDAC, i10nm: Fix randconfig builds
  EDAC, i10nm: Add a driver for Intel 10nm server processors
  EDAC, skx_edac: Delete duplicated code
  EDAC, skx_common: Separate common code out from skx_edac
  EDAC: Do not check return value of debugfs_create() functions
  EDAC: Add James Morse as a reviewer
  dt-bindings, EDAC: Add Aspeed AST2500
  EDAC, aspeed: Add an Aspeed AST2500 EDAC driver
parents c6400e5c 580b5cf5

Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt

0 → 100644
+25 −0
Original line number Diff line number Diff line 
Aspeed AST2500 SoC EDAC node



The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error

correction check).



The memory controller supports SECDED (single bit error correction, double bit

error detection) and single bit error auto scrubbing by reserving 8 bits for

every 64 bit word (effectively reducing available memory to 8/9).



Note, the bootloader must configure ECC mode in the memory controller.





Required properties:

- compatible: should be "aspeed,ast2500-sdram-edac"

- reg:        sdram controller register set should be <0x1e6e0000 0x174>

- interrupts: should be AVIC interrupt #0





Example:



	edac: sdram@1e6e0000 {

		compatible = "aspeed,ast2500-sdram-edac";

		reg = <0x1e6e0000 0x174>;

		interrupts = <0>;

	};

MAINTAINERS

+7 −0
Original line number Diff line number Diff line
@@ -5503,6 +5503,12 @@ L: linux-edac@vger.kernel.org 
S:	Maintained

F:	drivers/edac/amd64_edac*



EDAC-AST2500

M:	Stefan Schaeckeler <sschaeck@cisco.com>

S:	Supported

F:	drivers/edac/aspeed_edac.c

F:	Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt



EDAC-CALXEDA

M:	Robert Richter <rric@kernel.org>

L:	linux-edac@vger.kernel.org
@@ -5527,6 +5533,7 @@ F: drivers/edac/thunderx_edac* 
EDAC-CORE

M:	Borislav Petkov <bp@alien8.de>

M:	Mauro Carvalho Chehab <mchehab@kernel.org>

R:	James Morse <james.morse@arm.com>

L:	linux-edac@vger.kernel.org

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git for-next

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac.git linux_next

arch/arm/boot/dts/aspeed-g5.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -47,6 +47,13 @@ 
		reg = <0x80000000 0>;

	};



	edac: sdram@1e6e0000 {

		compatible = "aspeed,ast2500-sdram-edac";

		reg = <0x1e6e0000 0x174>;

		interrupts = <0>;

		status = "disabled";

	};



	ahb {

		compatible = "simple-bus";

		#address-cells = <1>;

drivers/edac/Kconfig

+32 −3
Original line number Diff line number Diff line
@@ -241,6 +241,18 @@ config EDAC_SKX 
	  system has non-volatile DIMMs you should also manually

	  select CONFIG_ACPI_NFIT.



config EDAC_I10NM

	tristate "Intel 10nm server Integrated MC"

	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI

	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y

	select DMI

	select ACPI_ADXL

	help

	  Support for error detection and correction the Intel

	  10nm server Integrated Memory Controllers. If your

	  system has non-volatile DIMMs you should also manually

	  select CONFIG_ACPI_NFIT.



config EDAC_PND2

	tristate "Intel Pondicherry2"

	depends on PCI && X86_64 && X86_MCE_INTEL
@@ -379,9 +391,17 @@ config EDAC_ALTERA 
	depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)

	help

	  Support for error detection and correction on the

	  Altera SOCs. This must be selected for SDRAM ECC.

	  Note that the preloader must initialize the SDRAM

	  before loading the kernel.

	  Altera SOCs. This is the global enable for the

	  various Altera peripherals.



config EDAC_ALTERA_SDRAM

	bool "Altera SDRAM ECC"

	depends on EDAC_ALTERA=y

	help

	  Support for error detection and correction on the

	  Altera SDRAM Memory for Altera SoCs. Note that the

	  preloader must initialize the SDRAM before loading

	  the kernel.



config EDAC_ALTERA_L2C

	bool "Altera L2 Cache ECC"
@@ -475,4 +495,13 @@ config EDAC_QCOM 
	  For debugging issues having to do with stability and overall system

	  health, you should probably say 'Y' here.



config EDAC_ASPEED

	tristate "Aspeed AST 2500 SoC"

	depends on MACH_ASPEED_G5

	help

	  Support for error detection and correction on the Aspeed AST 2500 SoC.



	  First, ECC must be configured in the bootloader. Then, this driver

	  will expose error counters via the EDAC kernel framework.



endif # EDAC

drivers/edac/Makefile

+7 −1
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ obj-$(CONFIG_EDAC_I5400) += i5400_edac.o 
obj-$(CONFIG_EDAC_I7300)		+= i7300_edac.o

obj-$(CONFIG_EDAC_I7CORE)		+= i7core_edac.o

obj-$(CONFIG_EDAC_SBRIDGE)		+= sb_edac.o

obj-$(CONFIG_EDAC_SKX)			+= skx_edac.o

obj-$(CONFIG_EDAC_PND2)			+= pnd2_edac.o

obj-$(CONFIG_EDAC_E7XXX)		+= e7xxx_edac.o

obj-$(CONFIG_EDAC_E752X)		+= e752x_edac.o
@@ -58,6 +57,12 @@ obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o 
layerscape_edac_mod-y			:= fsl_ddr_edac.o layerscape_edac.o

obj-$(CONFIG_EDAC_LAYERSCAPE)		+= layerscape_edac_mod.o



skx_edac-y				:= skx_common.o skx_base.o

obj-$(CONFIG_EDAC_SKX)			+= skx_edac.o



i10nm_edac-y				:= skx_common.o i10nm_base.o

obj-$(CONFIG_EDAC_I10NM)		+= i10nm_edac.o



obj-$(CONFIG_EDAC_MV64X60)		+= mv64x60_edac.o

obj-$(CONFIG_EDAC_CELL)			+= cell_edac.o

obj-$(CONFIG_EDAC_PPC4XX)		+= ppc4xx_edac.o
@@ -78,3 +83,4 @@ obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o 
obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o

obj-$(CONFIG_EDAC_TI)			+= ti_edac.o

obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o

obj-$(CONFIG_EDAC_ASPEED)		+= aspeed_edac.o

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