ARM: NOMMU: Set ARM_DMA_MEM_BUFFERABLE for M-class cpus (1b11d39e) · Commits · 戴 / test

Now, we have dedicated non-cacheable region for consistent DMA operations. However, that region can still be marked as bufferable by MPU, so it'd be safer to have barriers by default. M-class machines that didn't need it until now also likely won't need it in the future, therefore, we offer this as an option. Tested-by:

Benjamin Gaignard <benjamin.gaignard@linaro.org> Tested-by:

Andras Szemzo <sza@esh.hu> Tested-by:

Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by:

Robin Murphy <robin.murphy@arm.com> Signed-off-by:

Vladimir Murzin <vladimir.murzin@arm.com> Acked-by:

Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:

Christoph Hellwig <hch@lst.de>

arch/arm/mm/Kconfig

+6 −2

Original line number	Diff line number	Diff line
		@@ -1045,8 +1045,8 @@ config ARM_L1_CACHE_SHIFT
		default 5

		config ARM_DMA_MEM_BUFFERABLE
		bool "Use non-cacheable memory for DMA" if (CPU_V6 \|\| CPU_V6K) && !CPU_V7
		default y if CPU_V6 \|\| CPU_V6K \|\| CPU_V7
		bool "Use non-cacheable memory for DMA" if (CPU_V6 \|\| CPU_V6K \|\| CPU_V7M) && !CPU_V7
		default y if CPU_V6 \|\| CPU_V6K \|\| CPU_V7 \|\| CPU_V7M
		help
		Historically, the kernel has used strongly ordered mappings to
		provide DMA coherent memory. With the advent of ARMv7, mapping
		@@ -1061,6 +1061,10 @@ config ARM_DMA_MEM_BUFFERABLE
		and therefore turning this on may result in unpredictable driver
		behaviour. Therefore, we offer this as an option.

		On some of the beefier ARMv7-M machines (with DMA and write
		buffers) you likely want this enabled, while those that
		didn't need it until now also won't need it in the future.

		You are recommended say 'Y' here and debug any affected drivers.

		config ARM_HEAVY_MB

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