Commit 1ae39d65 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mediatek-next' 



Sean Wang says:

====================
net-next: mediatek: add support for ethernet on MT7622 SoC

Changes since v2:
- update John's mail

Changes since v1:
- add refinement for ethernet clock management
- take out the code block for ESW, add it until ESW driver is actually introduced

The series adds the driver for ethernet controller found on MT7622 SoC.
There are additions against with previous MT7623 SoC such as shared SGMII
given for the dual GMACs and built-in 5-ports 10/100 embedded switch support
(ESW). Thus more clocks consumers and SGMII hardware setup for the extra
features are all introduced here and as for the support for ESW that would be
planned to add in the separate patch integrating with DSA infrastructure
in the future.

Currently testing successfully is done with those patches for the conditions
such as GMAC2 with IP1001 PHY via RGMII and GMAC1/2 with RTL8211F PHY via SGMII.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2e674381 0857d6f8

Documentation/devicetree/bindings/net/mediatek-net.txt

+9 −3
Original line number Diff line number Diff line
@@ -7,24 +7,30 @@ have dual GMAC each represented by a child node.. 
* Ethernet controller node



Required properties:

- compatible: Should be "mediatek,mt2701-eth"

- compatible: Should be

		"mediatek,mt2701-eth": for MT2701 SoC

		"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC

		"mediatek,mt7622-eth": for MT7622 SoC

- reg: Address and length of the register set for the device

- interrupts: Should contain the three frame engines interrupts in numeric

	order. These are fe_int0, fe_int1 and fe_int2.

- clocks: the clock used by the core

- clock-names: the names of the clock listed in the clocks property. These are

	"ethif", "esw", "gp2", "gp1"

	"ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC

        "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",

	"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC

- power-domains: phandle to the power domain that the ethernet is part of

- resets: Should contain a phandle to the ethsys reset signal

- reset-names: Should contain the reset signal name "eth"

- mediatek,ethsys: phandle to the syscon node that handles the port setup

- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup

	which is required for those SoCs equipped with SGMII such as MT7622 SoC.

- mediatek,pctl: phandle to the syscon node that handles the ports slew rate

	and driver current



Optional properties:

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device



* Ethernet MAC node



Required properties:

MAINTAINERS

+3 −1
Original line number Diff line number Diff line
@@ -8425,7 +8425,9 @@ F: include/uapi/linux/uvcvideo.h 


MEDIATEK ETHERNET DRIVER

M:	Felix Fietkau <nbd@openwrt.org>

M:	John Crispin <blogic@openwrt.org>

M:	John Crispin <john@phrozen.org>

M:	Sean Wang <sean.wang@mediatek.com>

M:	Nelson Chang <nelson.chang@mediatek.com>

L:	netdev@vger.kernel.org

S:	Maintained

F:	drivers/net/ethernet/mediatek/

drivers/net/ethernet/mediatek/Kconfig

+3 −3
Original line number Diff line number Diff line
@@ -7,11 +7,11 @@ config NET_VENDOR_MEDIATEK 
if NET_VENDOR_MEDIATEK



config NET_MEDIATEK_SOC

	tristate "MediaTek MT7623 Gigabit ethernet support"

	depends on NET_VENDOR_MEDIATEK && (MACH_MT7623 || MACH_MT2701)

	tristate "MediaTek SoC Gigabit Ethernet support"

	depends on NET_VENDOR_MEDIATEK

	select PHYLIB

	---help---

	  This driver supports the gigabit ethernet MACs in the

	  MediaTek MT2701/MT7623 chipset family.

	  MediaTek SoC family.



endif #NET_VENDOR_MEDIATEK

drivers/net/ethernet/mediatek/mtk_eth_soc.c

+128 −14
Original line number Diff line number Diff line
@@ -53,7 +53,8 @@ static const struct mtk_ethtool_stats { 
};



static const char * const mtk_clks_source_name[] = {

	"ethif", "esw", "gp1", "gp2", "trgpll"

	"ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",

	"sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"

};



void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
@@ -163,6 +164,47 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 
	mtk_w32(eth, val, TRGMII_TCK_CTRL);

}



static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)

{

	u32 val;



	/* Setup the link timer and QPHY power up inside SGMIISYS */

	regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,

		     SGMII_LINK_TIMER_DEFAULT);



	regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);

	val |= SGMII_REMOTE_FAULT_DIS;

	regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);



	regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);

	val |= SGMII_AN_RESTART;

	regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);



	regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);

	val &= ~SGMII_PHYA_PWD;

	regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);



	/* Determine MUX for which GMAC uses the SGMII interface */

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {

		regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);

		val &= ~SYSCFG0_SGMII_MASK;

		val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;

		regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);



		dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",

			 mac_id);

	}



	/* Setup the GMAC1 going through SGMII path when SoC also support

	 * ESW on GMAC1

	 */

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&

	    !mac_id) {

		mtk_w32(eth, 0, MTK_MAC_MISC);

		dev_info(eth->dev, "setup gmac1 going through sgmii");

	}

}



static void mtk_phy_link_adjust(struct net_device *dev)

{

	struct mtk_mac *mac = netdev_priv(dev);
@@ -185,7 +227,8 @@ static void mtk_phy_link_adjust(struct net_device *dev) 
		break;

	};



	if (mac->id == 0 && !mac->trgmii)

	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&

	    !mac->id && !mac->trgmii)

		mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);



	if (dev->phydev->link)
@@ -269,6 +312,7 @@ static int mtk_phy_connect(struct net_device *dev) 
	if (!np)

		return -ENODEV;



	mac->ge_mode = 0;

	switch (of_get_phy_mode(np)) {

	case PHY_INTERFACE_MODE_TRGMII:

		mac->trgmii = true;
@@ -276,7 +320,10 @@ static int mtk_phy_connect(struct net_device *dev) 
	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII:

		mac->ge_mode = 0;

		break;

	case PHY_INTERFACE_MODE_SGMII:

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))

			mtk_gmac_sgmii_hw_setup(eth, mac->id);

		break;

	case PHY_INTERFACE_MODE_MII:

		mac->ge_mode = 1;
@@ -1834,9 +1881,36 @@ static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 
	mdelay(10);

}



static void mtk_clk_disable(struct mtk_eth *eth)

{

	int clk;



	for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)

		clk_disable_unprepare(eth->clks[clk]);

}



static int mtk_clk_enable(struct mtk_eth *eth)

{

	int clk, ret;



	for (clk = 0; clk < MTK_CLK_MAX ; clk++) {

		ret = clk_prepare_enable(eth->clks[clk]);

		if (ret)

			goto err_disable_clks;

	}



	return 0;



err_disable_clks:

	while (--clk >= 0)

		clk_disable_unprepare(eth->clks[clk]);



	return ret;

}



static int mtk_hw_init(struct mtk_eth *eth)

{

	int i, val;

	int i, val, ret;



	if (test_and_set_bit(MTK_HW_INIT, &eth->state))

		return 0;
@@ -1844,10 +1918,10 @@ static int mtk_hw_init(struct mtk_eth *eth) 
	pm_runtime_enable(eth->dev);

	pm_runtime_get_sync(eth->dev);



	clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);

	clk_prepare_enable(eth->clks[MTK_CLK_ESW]);

	clk_prepare_enable(eth->clks[MTK_CLK_GP1]);

	clk_prepare_enable(eth->clks[MTK_CLK_GP2]);

	ret = mtk_clk_enable(eth);

	if (ret)

		goto err_disable_pm;



	ethsys_reset(eth, RSTCTRL_FE);

	ethsys_reset(eth, RSTCTRL_PPE);
@@ -1915,6 +1989,12 @@ static int mtk_hw_init(struct mtk_eth *eth) 
	}



	return 0;



err_disable_pm:

	pm_runtime_put_sync(eth->dev);

	pm_runtime_disable(eth->dev);



	return ret;

}



static int mtk_hw_deinit(struct mtk_eth *eth)
@@ -1922,10 +2002,7 @@ static int mtk_hw_deinit(struct mtk_eth *eth) 
	if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))

		return 0;



	clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);

	clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);

	clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);

	clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);

	mtk_clk_disable(eth);



	pm_runtime_put_sync(eth->dev);

	pm_runtime_disable(eth->dev);
@@ -2392,6 +2469,7 @@ static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id) 
static bool mtk_is_hwlro_supported(struct mtk_eth *eth)

{

	switch (eth->chip_id) {

	case MT7622_ETH:

	case MT7623_ETH:

		return true;

	}
@@ -2403,6 +2481,7 @@ static int mtk_probe(struct platform_device *pdev) 
{

	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	struct device_node *mac_np;

	const struct of_device_id *match;

	struct mtk_eth *eth;

	int err;

	int i;
@@ -2411,6 +2490,9 @@ static int mtk_probe(struct platform_device *pdev) 
	if (!eth)

		return -ENOMEM;



	match = of_match_device(of_mtk_match, &pdev->dev);

	eth->soc = (struct mtk_soc_data *)match->data;



	eth->dev = &pdev->dev;

	eth->base = devm_ioremap_resource(&pdev->dev, res);

	if (IS_ERR(eth->base))
@@ -2427,6 +2509,16 @@ static int mtk_probe(struct platform_device *pdev) 
		return PTR_ERR(eth->ethsys);

	}



	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {

		eth->sgmiisys =

		syscon_regmap_lookup_by_phandle(pdev->dev.of_node,

						"mediatek,sgmiisys");

		if (IS_ERR(eth->sgmiisys)) {

			dev_err(&pdev->dev, "no sgmiisys regmap found\n");

			return PTR_ERR(eth->sgmiisys);

		}

	}



	eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,

						    "mediatek,pctl");

	if (IS_ERR(eth->pctl)) {
@@ -2447,7 +2539,12 @@ static int mtk_probe(struct platform_device *pdev) 
		if (IS_ERR(eth->clks[i])) {

			if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)

				return -EPROBE_DEFER;

			return -ENODEV;

			if (eth->soc->required_clks & BIT(i)) {

				dev_err(&pdev->dev, "clock %s not found\n",

					mtk_clks_source_name[i]);

				return -EINVAL;

			}

			eth->clks[i] = NULL;

		}

	}
@@ -2550,8 +2647,25 @@ static int mtk_remove(struct platform_device *pdev) 
	return 0;

}



static const struct mtk_soc_data mt2701_data = {

	.caps = MTK_GMAC1_TRGMII,

	.required_clks = MT7623_CLKS_BITMAP

};



static const struct mtk_soc_data mt7622_data = {

	.caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,

	.required_clks = MT7622_CLKS_BITMAP

};



static const struct mtk_soc_data mt7623_data = {

	.caps = MTK_GMAC1_TRGMII,

	.required_clks = MT7623_CLKS_BITMAP

};



const struct of_device_id of_mtk_match[] = {

	{ .compatible = "mediatek,mt2701-eth" },

	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},

	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},

	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},

	{},

};

MODULE_DEVICE_TABLE(of, of_mtk_match);

drivers/net/ethernet/mediatek/mtk_eth_soc.h

+72 −1
Original line number Diff line number Diff line
@@ -302,6 +302,9 @@ 
#define PHY_IAC_REG_SHIFT	25

#define PHY_IAC_TIMEOUT		HZ



#define MTK_MAC_MISC		0x1000c

#define MTK_MUX_TO_ESW		BIT(0)



/* Mac control registers */

#define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))

#define MAC_MCR_MAX_RX_1536	BIT(24)
@@ -357,11 +360,15 @@ 
#define ETHSYS_CHIPID0_3	0x0

#define ETHSYS_CHIPID4_7	0x4

#define MT7623_ETH		7623

#define MT7622_ETH		7622



/* ethernet subsystem config register */

#define ETHSYS_SYSCFG0		0x14

#define SYSCFG0_GE_MASK		0x3

#define SYSCFG0_GE_MODE(x, y)	(x << (12 + (y * 2)))

#define SYSCFG0_SGMII_MASK	(3 << 8)

#define SYSCFG0_SGMII_GMAC1	((2 << 8) & GENMASK(9, 8))

#define SYSCFG0_SGMII_GMAC2	((3 << 8) & GENMASK(9, 8))



/* ethernet subsystem clock register */

#define ETHSYS_CLKCFG0		0x2c
@@ -372,6 +379,23 @@ 
#define RSTCTRL_FE		BIT(6)

#define RSTCTRL_PPE		BIT(31)



/* SGMII subsystem config registers */

/* Register to auto-negotiation restart */

#define SGMSYS_PCS_CONTROL_1	0x0

#define SGMII_AN_RESTART	BIT(9)



/* Register to programmable link timer, the unit in 2 * 8ns */

#define SGMSYS_PCS_LINK_TIMER	0x18

#define SGMII_LINK_TIMER_DEFAULT	(0x186a0 & GENMASK(19, 0))



/* Register to control remote fault */

#define SGMSYS_SGMII_MODE	0x20

#define SGMII_REMOTE_FAULT_DIS	BIT(8)



/* Register to power up QPHY */

#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8

#define	SGMII_PHYA_PWD		BIT(4)



struct mtk_rx_dma {

	unsigned int rxd1;

	unsigned int rxd2;
@@ -437,12 +461,31 @@ enum mtk_tx_flags { 
enum mtk_clks_map {

	MTK_CLK_ETHIF,

	MTK_CLK_ESW,

	MTK_CLK_GP0,

	MTK_CLK_GP1,

	MTK_CLK_GP2,

	MTK_CLK_TRGPLL,

	MTK_CLK_SGMII_TX_250M,

	MTK_CLK_SGMII_RX_250M,

	MTK_CLK_SGMII_CDR_REF,

	MTK_CLK_SGMII_CDR_FB,

	MTK_CLK_SGMII_CK,

	MTK_CLK_ETH2PLL,

	MTK_CLK_MAX

};



#define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \

				 BIT(MTK_CLK_TRGPLL))

#define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_GP2) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII_CK) | \

				 BIT(MTK_CLK_ETH2PLL))

enum mtk_dev_state {

	MTK_HW_INIT,

	MTK_RESETTING
@@ -511,6 +554,28 @@ struct mtk_rx_ring { 
	u32 crx_idx_reg;

};



#define MTK_TRGMII			BIT(0)

#define MTK_GMAC1_TRGMII		(BIT(1) | MTK_TRGMII)

#define MTK_ESW				BIT(4)

#define MTK_GMAC1_ESW			(BIT(5) | MTK_ESW)

#define MTK_SGMII			BIT(8)

#define MTK_GMAC1_SGMII			(BIT(9) | MTK_SGMII)

#define MTK_GMAC2_SGMII			(BIT(10) | MTK_SGMII)

#define MTK_DUAL_GMAC_SHARED_SGMII	(BIT(11) | MTK_GMAC1_SGMII | \

					 MTK_GMAC2_SGMII)

#define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))



/* struct mtk_eth_data -	This is the structure holding all differences

 *				among various plaforms

 * @caps			Flags shown the extra capability for the SoC

 * @required_clks		Flags shown the bitmap for required clocks on

 *				the target SoC

 */

struct mtk_soc_data {

	u32		caps;

	u32		required_clks;

};



/* currently no SoC has more than 2 macs */

#define MTK_MAX_DEVS			2
@@ -529,6 +594,8 @@ struct mtk_rx_ring { 
 * @msg_enable:		Ethtool msg level

 * @ethsys:		The register map pointing at the range used to setup

 *			MII modes

 * @sgmiisys:		The register map pointing at the range used to setup

 *			SGMII modes

 * @pctl:		The register map pointing at the range used to setup

 *			GMAC port drive/slew values

 * @dma_refcnt:		track how many netdevs are using the DMA engine
@@ -542,7 +609,8 @@ struct mtk_rx_ring { 
 * @clks:		clock array for all clocks required

 * @mii_bus:		If there is a bus we need to create an instance for it

 * @pending_work:	The workqueue used to reset the dma ring

 * @state               Initialization and runtime state of the device.

 * @state:		Initialization and runtime state of the device

 * @soc:		Holding specific data among vaious SoCs

 */



struct mtk_eth {
@@ -558,6 +626,7 @@ struct mtk_eth { 
	u32				msg_enable;

	unsigned long			sysclk;

	struct regmap			*ethsys;

	struct regmap			*sgmiisys;

	struct regmap			*pctl;

	u32				chip_id;

	bool				hwlro;
@@ -574,6 +643,8 @@ struct mtk_eth { 
	struct mii_bus			*mii_bus;

	struct work_struct		pending_work;

	unsigned long			state;



	const struct mtk_soc_data	*soc;

};



/* struct mtk_mac -	the structure that holds the info about the MACs of the

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